/*
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* Copyright 2015 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs <bskeggs@redhat.com>
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*/
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#include "gf100.h"
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#include "ctxgf100.h"
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#include <subdev/secboot.h>
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#include <nvif/class.h>
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/*******************************************************************************
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* PGRAPH engine/subdev functions
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******************************************************************************/
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int
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gm200_gr_rops(struct gf100_gr *gr)
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{
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return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c);
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}
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void
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gm200_gr_init_ds_hww_esr_2(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, 0x405848, 0xc0000000);
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nvkm_mask(device, 0x40584c, 0x00000001, 0x00000001);
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}
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void
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gm200_gr_init_num_active_ltcs(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
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nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804));
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}
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void
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gm200_gr_init_gpc_mmu(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf0001fff);
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nvkm_wr32(device, 0x418890, 0x00000000);
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nvkm_wr32(device, 0x418894, 0x00000000);
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nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
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nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
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nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
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}
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static void
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gm200_gr_init_rop_active_fbps(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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const u32 fbp_count = nvkm_rd32(device, 0x12006c);
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nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
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nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
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}
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static u8
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gm200_gr_tile_map_6_24[] = {
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0, 1, 2, 3, 4, 5, 3, 4, 5, 0, 1, 2, 0, 1, 2, 3, 4, 5, 3, 4, 5, 0, 1, 2,
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};
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static u8
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gm200_gr_tile_map_4_16[] = {
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0, 1, 2, 3, 2, 3, 0, 1, 3, 0, 1, 2, 1, 2, 3, 0,
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};
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static u8
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gm200_gr_tile_map_2_8[] = {
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0, 1, 1, 0, 0, 1, 1, 0,
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};
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void
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gm200_gr_oneinit_sm_id(struct gf100_gr *gr)
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{
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/*XXX: There's a different algorithm here I've not yet figured out. */
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gf100_gr_oneinit_sm_id(gr);
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}
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void
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gm200_gr_oneinit_tiles(struct gf100_gr *gr)
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{
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/*XXX: Not sure what this is about. The algorithm from NVGPU
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* seems to work for all boards I tried from earlier (and
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* later) GPUs except in these specific configurations.
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*
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* Let's just hardcode them for now.
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*/
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if (gr->gpc_nr == 2 && gr->tpc_total == 8) {
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memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total);
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gr->screen_tile_row_offset = 1;
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} else
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if (gr->gpc_nr == 4 && gr->tpc_total == 16) {
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memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total);
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gr->screen_tile_row_offset = 4;
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} else
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if (gr->gpc_nr == 6 && gr->tpc_total == 24) {
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memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total);
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gr->screen_tile_row_offset = 5;
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} else {
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gf100_gr_oneinit_tiles(gr);
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}
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}
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int
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gm200_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
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int index, struct nvkm_gr **pgr)
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{
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struct gf100_gr *gr;
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int ret;
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if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
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return -ENOMEM;
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*pgr = &gr->base;
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ret = gf100_gr_ctor(func, device, index, gr);
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if (ret)
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return ret;
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/* Load firmwares for non-secure falcons */
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if (!nvkm_secboot_is_managed(device->secboot,
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NVKM_SECBOOT_FALCON_FECS)) {
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if ((ret = gf100_gr_ctor_fw(gr, "gr/fecs_inst", &gr->fuc409c)) ||
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(ret = gf100_gr_ctor_fw(gr, "gr/fecs_data", &gr->fuc409d)))
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return ret;
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}
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if (!nvkm_secboot_is_managed(device->secboot,
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NVKM_SECBOOT_FALCON_GPCCS)) {
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if ((ret = gf100_gr_ctor_fw(gr, "gr/gpccs_inst", &gr->fuc41ac)) ||
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(ret = gf100_gr_ctor_fw(gr, "gr/gpccs_data", &gr->fuc41ad)))
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return ret;
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}
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if ((ret = gk20a_gr_av_to_init(gr, "gr/sw_nonctx", &gr->fuc_sw_nonctx)) ||
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(ret = gk20a_gr_aiv_to_init(gr, "gr/sw_ctx", &gr->fuc_sw_ctx)) ||
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(ret = gk20a_gr_av_to_init(gr, "gr/sw_bundle_init", &gr->fuc_bundle)) ||
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(ret = gk20a_gr_av_to_method(gr, "gr/sw_method_init", &gr->fuc_method)))
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return ret;
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return 0;
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}
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static const struct gf100_gr_func
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gm200_gr = {
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.oneinit_tiles = gm200_gr_oneinit_tiles,
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.oneinit_sm_id = gm200_gr_oneinit_sm_id,
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.init = gf100_gr_init,
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.init_gpc_mmu = gm200_gr_init_gpc_mmu,
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.init_bios = gm107_gr_init_bios,
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.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
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.init_zcull = gf117_gr_init_zcull,
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.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
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.init_rop_active_fbps = gm200_gr_init_rop_active_fbps,
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.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
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.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
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.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
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.init_419cc0 = gf100_gr_init_419cc0,
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.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
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.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
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.init_504430 = gm107_gr_init_504430,
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.init_shader_exceptions = gm107_gr_init_shader_exceptions,
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.init_400054 = gm107_gr_init_400054,
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.trap_mp = gf100_gr_trap_mp,
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.rops = gm200_gr_rops,
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.tpc_nr = 4,
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.ppc_nr = 2,
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.grctx = &gm200_grctx,
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.zbc = &gf100_gr_zbc,
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.sclass = {
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{ -1, -1, FERMI_TWOD_A },
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{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
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{ -1, -1, MAXWELL_B, &gf100_fermi },
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{ -1, -1, MAXWELL_COMPUTE_B },
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{}
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}
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};
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int
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gm200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
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{
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return gm200_gr_new_(&gm200_gr, device, index, pgr);
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}
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