/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __NVIF_CL0080_H__
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#define __NVIF_CL0080_H__
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struct nv_device_v0 {
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__u8 version;
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__u8 pad01[7];
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__u64 device; /* device identifier, ~0 for client default */
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};
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#define NV_DEVICE_V0_INFO 0x00
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#define NV_DEVICE_V0_TIME 0x01
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struct nv_device_info_v0 {
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__u8 version;
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#define NV_DEVICE_INFO_V0_IGP 0x00
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#define NV_DEVICE_INFO_V0_PCI 0x01
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#define NV_DEVICE_INFO_V0_AGP 0x02
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#define NV_DEVICE_INFO_V0_PCIE 0x03
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#define NV_DEVICE_INFO_V0_SOC 0x04
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__u8 platform;
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__u16 chipset; /* from NV_PMC_BOOT_0 */
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__u8 revision; /* from NV_PMC_BOOT_0 */
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#define NV_DEVICE_INFO_V0_TNT 0x01
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#define NV_DEVICE_INFO_V0_CELSIUS 0x02
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#define NV_DEVICE_INFO_V0_KELVIN 0x03
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#define NV_DEVICE_INFO_V0_RANKINE 0x04
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#define NV_DEVICE_INFO_V0_CURIE 0x05
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#define NV_DEVICE_INFO_V0_TESLA 0x06
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#define NV_DEVICE_INFO_V0_FERMI 0x07
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#define NV_DEVICE_INFO_V0_KEPLER 0x08
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#define NV_DEVICE_INFO_V0_MAXWELL 0x09
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#define NV_DEVICE_INFO_V0_PASCAL 0x0a
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#define NV_DEVICE_INFO_V0_VOLTA 0x0b
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__u8 family;
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__u8 pad06[2];
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__u64 ram_size;
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__u64 ram_user;
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char chip[16];
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char name[64];
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};
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struct nv_device_info_v1 {
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__u8 version;
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__u8 count;
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__u8 pad02[6];
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struct nv_device_info_v1_data {
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__u64 mthd; /* NV_DEVICE_INFO_* (see below). */
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__u64 data;
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} data[];
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};
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struct nv_device_time_v0 {
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__u8 version;
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__u8 pad01[7];
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__u64 time;
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};
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#define NV_DEVICE_INFO_UNIT (0xffffffffULL << 32)
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#define NV_DEVICE_INFO(n) ((n) | (0x00000000ULL << 32))
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#define NV_DEVICE_FIFO(n) ((n) | (0x00000001ULL << 32))
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/* This will be returned for unsupported queries. */
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#define NV_DEVICE_INFO_INVALID ~0ULL
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/* These return a mask of available engines of particular type. */
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#define NV_DEVICE_INFO_ENGINE_SW NV_DEVICE_INFO(0x00000000)
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#define NV_DEVICE_INFO_ENGINE_GR NV_DEVICE_INFO(0x00000001)
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#define NV_DEVICE_INFO_ENGINE_MPEG NV_DEVICE_INFO(0x00000002)
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#define NV_DEVICE_INFO_ENGINE_ME NV_DEVICE_INFO(0x00000003)
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#define NV_DEVICE_INFO_ENGINE_CIPHER NV_DEVICE_INFO(0x00000004)
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#define NV_DEVICE_INFO_ENGINE_BSP NV_DEVICE_INFO(0x00000005)
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#define NV_DEVICE_INFO_ENGINE_VP NV_DEVICE_INFO(0x00000006)
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#define NV_DEVICE_INFO_ENGINE_CE NV_DEVICE_INFO(0x00000007)
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#define NV_DEVICE_INFO_ENGINE_SEC NV_DEVICE_INFO(0x00000008)
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#define NV_DEVICE_INFO_ENGINE_MSVLD NV_DEVICE_INFO(0x00000009)
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#define NV_DEVICE_INFO_ENGINE_MSPDEC NV_DEVICE_INFO(0x0000000a)
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#define NV_DEVICE_INFO_ENGINE_MSPPP NV_DEVICE_INFO(0x0000000b)
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#define NV_DEVICE_INFO_ENGINE_MSENC NV_DEVICE_INFO(0x0000000c)
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#define NV_DEVICE_INFO_ENGINE_VIC NV_DEVICE_INFO(0x0000000d)
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#define NV_DEVICE_INFO_ENGINE_SEC2 NV_DEVICE_INFO(0x0000000e)
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#define NV_DEVICE_INFO_ENGINE_NVDEC NV_DEVICE_INFO(0x0000000f)
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#define NV_DEVICE_INFO_ENGINE_NVENC NV_DEVICE_INFO(0x00000010)
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/* Returns the number of available channels. */
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#define NV_DEVICE_FIFO_CHANNELS NV_DEVICE_FIFO(0x00000000)
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/* Returns a mask of available runlists. */
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#define NV_DEVICE_FIFO_RUNLISTS NV_DEVICE_FIFO(0x00000001)
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/* These return a mask of engines available on a particular runlist. */
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#define NV_DEVICE_FIFO_RUNLIST_ENGINES(n) ((n) + NV_DEVICE_FIFO(0x00000010))
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#define NV_DEVICE_FIFO_RUNLIST_ENGINES__SIZE 64
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#endif
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