/*
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* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include "dsi_pll.h"
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#include "dsi.xml.h"
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/*
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* DSI PLL 28nm (8960/A family) - clock diagram (eg: DSI1):
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*
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*
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* +------+
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* dsi1vco_clk ----o-----| DIV1 |---dsi1pllbit (not exposed as clock)
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* F * byte_clk | +------+
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* | bit clock divider (F / 8)
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* |
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* | +------+
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* o-----| DIV2 |---dsi0pllbyte---o---> To byte RCG
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* | +------+ | (sets parent rate)
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* | byte clock divider (F) |
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* | |
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* | o---> To esc RCG
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* | (doesn't set parent rate)
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* |
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* | +------+
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* o-----| DIV3 |----dsi0pll------o---> To dsi RCG
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* +------+ | (sets parent rate)
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* dsi clock divider (F * magic) |
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* |
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* o---> To pixel rcg
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* (doesn't set parent rate)
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*/
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#define POLL_MAX_READS 8000
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#define POLL_TIMEOUT_US 1
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#define NUM_PROVIDED_CLKS 2
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#define VCO_REF_CLK_RATE 27000000
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#define VCO_MIN_RATE 600000000
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#define VCO_MAX_RATE 1200000000
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#define DSI_BYTE_PLL_CLK 0
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#define DSI_PIXEL_PLL_CLK 1
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#define VCO_PREF_DIV_RATIO 27
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struct pll_28nm_cached_state {
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unsigned long vco_rate;
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u8 postdiv3;
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u8 postdiv2;
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u8 postdiv1;
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};
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struct clk_bytediv {
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struct clk_hw hw;
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void __iomem *reg;
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};
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struct dsi_pll_28nm {
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struct msm_dsi_pll base;
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int id;
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struct platform_device *pdev;
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void __iomem *mmio;
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/* custom byte clock divider */
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struct clk_bytediv *bytediv;
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/* private clocks: */
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struct clk *clks[NUM_DSI_CLOCKS_MAX];
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u32 num_clks;
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/* clock-provider: */
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struct clk *provided_clks[NUM_PROVIDED_CLKS];
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struct clk_onecell_data clk_data;
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struct pll_28nm_cached_state cached_state;
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};
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#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base)
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static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
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int nb_tries, int timeout_us)
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{
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bool pll_locked = false;
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u32 val;
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while (nb_tries--) {
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val = pll_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY);
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pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY);
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if (pll_locked)
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break;
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udelay(timeout_us);
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}
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DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* ");
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return pll_locked;
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}
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/*
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* Clock Callbacks
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*/
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static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
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struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
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void __iomem *base = pll_28nm->mmio;
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u32 val, temp, fb_divider;
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DBG("rate=%lu, parent's=%lu", rate, parent_rate);
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temp = rate / 10;
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val = VCO_REF_CLK_RATE / 10;
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fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;
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fb_divider = fb_divider / 2 - 1;
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pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
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fb_divider & 0xff);
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val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2);
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val |= (fb_divider >> 8) & 0x07;
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pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2,
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val);
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val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
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val |= (VCO_PREF_DIV_RATIO - 1) & 0x3f;
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pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3,
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val);
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pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6,
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0xf);
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val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
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val |= 0x7 << 4;
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pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
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val);
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return 0;
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}
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static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
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{
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struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
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struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
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return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS,
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POLL_TIMEOUT_US);
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}
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static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
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struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
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void __iomem *base = pll_28nm->mmio;
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unsigned long vco_rate;
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u32 status, fb_divider, temp, ref_divider;
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VERB("parent_rate=%lu", parent_rate);
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status = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);
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if (status & DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE) {
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fb_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1);
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fb_divider &= 0xff;
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temp = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07;
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fb_divider = (temp << 8) | fb_divider;
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fb_divider += 1;
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ref_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
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ref_divider &= 0x3f;
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ref_divider += 1;
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/* multiply by 2 */
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vco_rate = (parent_rate / ref_divider) * fb_divider * 2;
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} else {
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vco_rate = 0;
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}
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DBG("returning vco rate = %lu", vco_rate);
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return vco_rate;
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}
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static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
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.round_rate = msm_dsi_pll_helper_clk_round_rate,
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.set_rate = dsi_pll_28nm_clk_set_rate,
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.recalc_rate = dsi_pll_28nm_clk_recalc_rate,
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.prepare = msm_dsi_pll_helper_clk_prepare,
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.unprepare = msm_dsi_pll_helper_clk_unprepare,
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.is_enabled = dsi_pll_28nm_clk_is_enabled,
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};
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/*
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* Custom byte clock divier clk_ops
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*
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* This clock is the entry point to configuring the PLL. The user (dsi host)
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* will set this clock's rate to the desired byte clock rate. The VCO lock
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* frequency is a multiple of the byte clock rate. The multiplication factor
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* (shown as F in the diagram above) is a function of the byte clock rate.
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*
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* This custom divider clock ensures that its parent (VCO) is set to the
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* desired rate, and that the byte clock postdivider (POSTDIV2) is configured
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* accordingly
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*/
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#define to_clk_bytediv(_hw) container_of(_hw, struct clk_bytediv, hw)
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static unsigned long clk_bytediv_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_bytediv *bytediv = to_clk_bytediv(hw);
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unsigned int div;
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div = pll_read(bytediv->reg) & 0xff;
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return parent_rate / (div + 1);
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}
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/* find multiplication factor(wrt byte clock) at which the VCO should be set */
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static unsigned int get_vco_mul_factor(unsigned long byte_clk_rate)
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{
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unsigned long bit_mhz;
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/* convert to bit clock in Mhz */
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bit_mhz = (byte_clk_rate * 8) / 1000000;
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if (bit_mhz < 125)
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return 64;
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else if (bit_mhz < 250)
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return 32;
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else if (bit_mhz < 600)
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return 16;
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else
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return 8;
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}
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static long clk_bytediv_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long best_parent;
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unsigned int factor;
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factor = get_vco_mul_factor(rate);
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best_parent = rate * factor;
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*prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
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return *prate / factor;
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}
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static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_bytediv *bytediv = to_clk_bytediv(hw);
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u32 val;
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unsigned int factor;
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factor = get_vco_mul_factor(rate);
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val = pll_read(bytediv->reg);
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val |= (factor - 1) & 0xff;
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pll_write(bytediv->reg, val);
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return 0;
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}
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/* Our special byte clock divider ops */
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static const struct clk_ops clk_bytediv_ops = {
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.round_rate = clk_bytediv_round_rate,
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.set_rate = clk_bytediv_set_rate,
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.recalc_rate = clk_bytediv_recalc_rate,
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};
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/*
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* PLL Callbacks
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*/
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static int dsi_pll_28nm_enable_seq(struct msm_dsi_pll *pll)
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{
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struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
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struct device *dev = &pll_28nm->pdev->dev;
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void __iomem *base = pll_28nm->mmio;
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bool locked;
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unsigned int bit_div, byte_div;
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int max_reads = 1000, timeout_us = 100;
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u32 val;
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DBG("id=%d", pll_28nm->id);
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/*
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* before enabling the PLL, configure the bit clock divider since we
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* don't expose it as a clock to the outside world
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* 1: read back the byte clock divider that should already be set
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* 2: divide by 8 to get bit clock divider
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* 3: write it to POSTDIV1
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*/
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val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
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byte_div = val + 1;
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bit_div = byte_div / 8;
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val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
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val &= ~0xf;
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val |= (bit_div - 1);
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pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
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/* enable the PLL */
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pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
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DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE);
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locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
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if (unlikely(!locked))
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dev_err(dev, "DSI PLL lock failed\n");
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else
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DBG("DSI PLL lock success");
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return locked ? 0 : -EINVAL;
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}
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static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll)
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{
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struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
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DBG("id=%d", pll_28nm->id);
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pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
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}
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static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
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{
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struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
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struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
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void __iomem *base = pll_28nm->mmio;
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cached_state->postdiv3 =
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pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);
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cached_state->postdiv2 =
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pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
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cached_state->postdiv1 =
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pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
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cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
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}
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static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
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{
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struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
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struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
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void __iomem *base = pll_28nm->mmio;
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int ret;
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ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw,
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cached_state->vco_rate, 0);
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if (ret) {
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dev_err(&pll_28nm->pdev->dev,
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"restore vco rate failed. ret=%d\n", ret);
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return ret;
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}
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pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
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cached_state->postdiv3);
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pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9,
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cached_state->postdiv2);
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pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
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cached_state->postdiv1);
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return 0;
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}
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static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll,
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struct clk **byte_clk_provider,
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struct clk **pixel_clk_provider)
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{
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struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
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if (byte_clk_provider)
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*byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK];
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if (pixel_clk_provider)
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*pixel_clk_provider =
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pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK];
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return 0;
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}
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static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
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{
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struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
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msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev,
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pll_28nm->clks, pll_28nm->num_clks);
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}
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static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
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{
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char *clk_name, *parent_name, *vco_name;
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struct clk_init_data vco_init = {
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.parent_names = (const char *[]){ "pxo" },
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.num_parents = 1,
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.flags = CLK_IGNORE_UNUSED,
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.ops = &clk_ops_dsi_pll_28nm_vco,
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};
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struct device *dev = &pll_28nm->pdev->dev;
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struct clk **clks = pll_28nm->clks;
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struct clk **provided_clks = pll_28nm->provided_clks;
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struct clk_bytediv *bytediv;
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struct clk_init_data bytediv_init = { };
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int ret, num = 0;
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DBG("%d", pll_28nm->id);
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bytediv = devm_kzalloc(dev, sizeof(*bytediv), GFP_KERNEL);
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if (!bytediv)
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return -ENOMEM;
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vco_name = devm_kzalloc(dev, 32, GFP_KERNEL);
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if (!vco_name)
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return -ENOMEM;
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parent_name = devm_kzalloc(dev, 32, GFP_KERNEL);
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if (!parent_name)
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return -ENOMEM;
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clk_name = devm_kzalloc(dev, 32, GFP_KERNEL);
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if (!clk_name)
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return -ENOMEM;
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pll_28nm->bytediv = bytediv;
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snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
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vco_init.name = vco_name;
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pll_28nm->base.clk_hw.init = &vco_init;
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clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw);
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/* prepare and register bytediv */
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bytediv->hw.init = &bytediv_init;
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bytediv->reg = pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_9;
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snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->id);
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snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
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bytediv_init.name = clk_name;
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bytediv_init.ops = &clk_bytediv_ops;
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bytediv_init.flags = CLK_SET_RATE_PARENT;
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bytediv_init.parent_names = (const char * const *) &parent_name;
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bytediv_init.num_parents = 1;
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/* DIV2 */
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clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] =
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clk_register(dev, &bytediv->hw);
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snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
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/* DIV3 */
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clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] =
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clk_register_divider(dev, clk_name,
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parent_name, 0, pll_28nm->mmio +
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REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
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0, 8, 0, NULL);
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pll_28nm->num_clks = num;
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pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS;
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pll_28nm->clk_data.clks = provided_clks;
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ret = of_clk_add_provider(dev->of_node,
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of_clk_src_onecell_get, &pll_28nm->clk_data);
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if (ret) {
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dev_err(dev, "failed to register clk provider: %d\n", ret);
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return ret;
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}
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return 0;
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}
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struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
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int id)
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{
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struct dsi_pll_28nm *pll_28nm;
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struct msm_dsi_pll *pll;
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int ret;
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if (!pdev)
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return ERR_PTR(-ENODEV);
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pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL);
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if (!pll_28nm)
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return ERR_PTR(-ENOMEM);
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pll_28nm->pdev = pdev;
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pll_28nm->id = id + 1;
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pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
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if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
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dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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pll = &pll_28nm->base;
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pll->min_rate = VCO_MIN_RATE;
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pll->max_rate = VCO_MAX_RATE;
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pll->get_provider = dsi_pll_28nm_get_provider;
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pll->destroy = dsi_pll_28nm_destroy;
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pll->disable_seq = dsi_pll_28nm_disable_seq;
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pll->save_state = dsi_pll_28nm_save_state;
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pll->restore_state = dsi_pll_28nm_restore_state;
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pll->en_seq_cnt = 1;
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pll->enable_seqs[0] = dsi_pll_28nm_enable_seq;
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ret = pll_28nm_register(pll_28nm);
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if (ret) {
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dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
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return ERR_PTR(ret);
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}
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return pll;
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}
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