/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "dm_services.h"
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/* include DCE11 register header files */
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#include "dce/dce_11_0_d.h"
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#include "dce/dce_11_0_sh_mask.h"
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#include "dc_types.h"
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#include "dc_bios_types.h"
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#include "dc.h"
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#include "include/grph_object_id.h"
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#include "include/logger_interface.h"
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#include "dce110_timing_generator.h"
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#include "dce110_timing_generator_v.h"
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#include "timing_generator.h"
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#define DC_LOGGER \
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tg->ctx->logger
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/** ********************************************************************************
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*
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* DCE11 Timing Generator Implementation
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*
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**********************************************************************************/
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/**
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* Enable CRTCV
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*/
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static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg)
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{
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/*
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* Set MASTER_UPDATE_MODE to 0
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* This is needed for DRR, and also suggested to be default value by Syed.
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*/
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uint32_t value;
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value = 0;
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set_reg_field_value(value, 0,
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CRTCV_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE);
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dm_write_reg(tg->ctx,
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mmCRTCV_MASTER_UPDATE_MODE, value);
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/* TODO: may want this on for looking for underflow */
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value = 0;
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dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value);
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value = 0;
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set_reg_field_value(value, 1,
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CRTCV_MASTER_EN, CRTC_MASTER_EN);
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dm_write_reg(tg->ctx,
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mmCRTCV_MASTER_EN, value);
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return true;
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}
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static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg)
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{
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uint32_t value;
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value = dm_read_reg(tg->ctx,
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mmCRTCV_CONTROL);
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set_reg_field_value(value, 0,
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CRTCV_CONTROL, CRTC_DISABLE_POINT_CNTL);
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set_reg_field_value(value, 0,
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CRTCV_CONTROL, CRTC_MASTER_EN);
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dm_write_reg(tg->ctx,
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mmCRTCV_CONTROL, value);
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/*
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* TODO: call this when adding stereo support
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* tg->funcs->disable_stereo(tg);
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*/
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return true;
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}
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static void dce110_timing_generator_v_blank_crtc(struct timing_generator *tg)
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{
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uint32_t addr = mmCRTCV_BLANK_CONTROL;
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uint32_t value = dm_read_reg(tg->ctx, addr);
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set_reg_field_value(
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value,
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1,
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CRTCV_BLANK_CONTROL,
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CRTC_BLANK_DATA_EN);
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set_reg_field_value(
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value,
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0,
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CRTCV_BLANK_CONTROL,
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CRTC_BLANK_DE_MODE);
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dm_write_reg(tg->ctx, addr, value);
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}
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static void dce110_timing_generator_v_unblank_crtc(struct timing_generator *tg)
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{
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uint32_t addr = mmCRTCV_BLANK_CONTROL;
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uint32_t value = dm_read_reg(tg->ctx, addr);
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set_reg_field_value(
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value,
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0,
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CRTCV_BLANK_CONTROL,
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CRTC_BLANK_DATA_EN);
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set_reg_field_value(
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value,
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0,
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CRTCV_BLANK_CONTROL,
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CRTC_BLANK_DE_MODE);
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dm_write_reg(tg->ctx, addr, value);
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}
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static bool dce110_timing_generator_v_is_in_vertical_blank(
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struct timing_generator *tg)
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{
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uint32_t addr = 0;
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uint32_t value = 0;
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uint32_t field = 0;
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addr = mmCRTCV_STATUS;
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value = dm_read_reg(tg->ctx, addr);
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field = get_reg_field_value(value, CRTCV_STATUS, CRTC_V_BLANK);
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return field == 1;
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}
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static bool dce110_timing_generator_v_is_counter_moving(struct timing_generator *tg)
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{
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uint32_t value;
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uint32_t h1 = 0;
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uint32_t h2 = 0;
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uint32_t v1 = 0;
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uint32_t v2 = 0;
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value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION);
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h1 = get_reg_field_value(
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value,
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CRTCV_STATUS_POSITION,
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CRTC_HORZ_COUNT);
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v1 = get_reg_field_value(
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value,
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CRTCV_STATUS_POSITION,
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CRTC_VERT_COUNT);
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value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION);
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h2 = get_reg_field_value(
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value,
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CRTCV_STATUS_POSITION,
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CRTC_HORZ_COUNT);
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v2 = get_reg_field_value(
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value,
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CRTCV_STATUS_POSITION,
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CRTC_VERT_COUNT);
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if (h1 == h2 && v1 == v2)
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return false;
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else
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return true;
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}
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static void dce110_timing_generator_v_wait_for_vblank(struct timing_generator *tg)
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{
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/* We want to catch beginning of VBlank here, so if the first try are
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* in VBlank, we might be very close to Active, in this case wait for
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* another frame
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*/
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while (dce110_timing_generator_v_is_in_vertical_blank(tg)) {
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if (!dce110_timing_generator_v_is_counter_moving(tg)) {
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/* error - no point to wait if counter is not moving */
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break;
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}
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}
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while (!dce110_timing_generator_v_is_in_vertical_blank(tg)) {
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if (!dce110_timing_generator_v_is_counter_moving(tg)) {
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/* error - no point to wait if counter is not moving */
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break;
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}
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}
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}
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/**
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* Wait till we are in VActive (anywhere in VActive)
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*/
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static void dce110_timing_generator_v_wait_for_vactive(struct timing_generator *tg)
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{
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while (dce110_timing_generator_v_is_in_vertical_blank(tg)) {
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if (!dce110_timing_generator_v_is_counter_moving(tg)) {
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/* error - no point to wait if counter is not moving */
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break;
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}
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}
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}
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static void dce110_timing_generator_v_wait_for_state(struct timing_generator *tg,
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enum crtc_state state)
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{
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switch (state) {
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case CRTC_STATE_VBLANK:
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dce110_timing_generator_v_wait_for_vblank(tg);
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break;
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case CRTC_STATE_VACTIVE:
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dce110_timing_generator_v_wait_for_vactive(tg);
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break;
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default:
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break;
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}
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}
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static void dce110_timing_generator_v_program_blanking(
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struct timing_generator *tg,
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const struct dc_crtc_timing *timing)
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{
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uint32_t vsync_offset = timing->v_border_bottom +
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timing->v_front_porch;
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uint32_t v_sync_start = timing->v_addressable + vsync_offset;
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uint32_t hsync_offset = timing->h_border_right +
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timing->h_front_porch;
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uint32_t h_sync_start = timing->h_addressable + hsync_offset;
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struct dc_context *ctx = tg->ctx;
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uint32_t value = 0;
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uint32_t addr = 0;
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uint32_t tmp = 0;
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addr = mmCRTCV_H_TOTAL;
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value = dm_read_reg(ctx, addr);
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set_reg_field_value(
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value,
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timing->h_total - 1,
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CRTCV_H_TOTAL,
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CRTC_H_TOTAL);
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dm_write_reg(ctx, addr, value);
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addr = mmCRTCV_V_TOTAL;
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value = dm_read_reg(ctx, addr);
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set_reg_field_value(
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value,
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timing->v_total - 1,
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CRTCV_V_TOTAL,
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CRTC_V_TOTAL);
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dm_write_reg(ctx, addr, value);
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addr = mmCRTCV_H_BLANK_START_END;
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value = dm_read_reg(ctx, addr);
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tmp = timing->h_total -
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(h_sync_start + timing->h_border_left);
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set_reg_field_value(
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value,
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tmp,
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CRTCV_H_BLANK_START_END,
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CRTC_H_BLANK_END);
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tmp = tmp + timing->h_addressable +
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timing->h_border_left + timing->h_border_right;
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set_reg_field_value(
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value,
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tmp,
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CRTCV_H_BLANK_START_END,
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CRTC_H_BLANK_START);
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dm_write_reg(ctx, addr, value);
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addr = mmCRTCV_V_BLANK_START_END;
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value = dm_read_reg(ctx, addr);
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tmp = timing->v_total - (v_sync_start + timing->v_border_top);
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set_reg_field_value(
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value,
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tmp,
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CRTCV_V_BLANK_START_END,
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CRTC_V_BLANK_END);
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tmp = tmp + timing->v_addressable + timing->v_border_top +
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timing->v_border_bottom;
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set_reg_field_value(
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value,
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tmp,
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CRTCV_V_BLANK_START_END,
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CRTC_V_BLANK_START);
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dm_write_reg(ctx, addr, value);
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addr = mmCRTCV_H_SYNC_A;
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value = 0;
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set_reg_field_value(
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value,
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timing->h_sync_width,
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CRTCV_H_SYNC_A,
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CRTC_H_SYNC_A_END);
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dm_write_reg(ctx, addr, value);
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addr = mmCRTCV_H_SYNC_A_CNTL;
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value = dm_read_reg(ctx, addr);
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if (timing->flags.HSYNC_POSITIVE_POLARITY) {
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set_reg_field_value(
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value,
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0,
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CRTCV_H_SYNC_A_CNTL,
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CRTC_H_SYNC_A_POL);
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} else {
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set_reg_field_value(
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value,
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1,
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CRTCV_H_SYNC_A_CNTL,
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CRTC_H_SYNC_A_POL);
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}
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dm_write_reg(ctx, addr, value);
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addr = mmCRTCV_V_SYNC_A;
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value = 0;
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set_reg_field_value(
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value,
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timing->v_sync_width,
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CRTCV_V_SYNC_A,
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CRTC_V_SYNC_A_END);
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dm_write_reg(ctx, addr, value);
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addr = mmCRTCV_V_SYNC_A_CNTL;
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value = dm_read_reg(ctx, addr);
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if (timing->flags.VSYNC_POSITIVE_POLARITY) {
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set_reg_field_value(
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value,
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0,
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CRTCV_V_SYNC_A_CNTL,
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CRTC_V_SYNC_A_POL);
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} else {
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set_reg_field_value(
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value,
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1,
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CRTCV_V_SYNC_A_CNTL,
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CRTC_V_SYNC_A_POL);
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}
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dm_write_reg(ctx, addr, value);
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addr = mmCRTCV_INTERLACE_CONTROL;
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value = dm_read_reg(ctx, addr);
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set_reg_field_value(
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value,
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timing->flags.INTERLACE,
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CRTCV_INTERLACE_CONTROL,
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CRTC_INTERLACE_ENABLE);
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dm_write_reg(ctx, addr, value);
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}
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static void dce110_timing_generator_v_enable_advanced_request(
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struct timing_generator *tg,
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bool enable,
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const struct dc_crtc_timing *timing)
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{
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uint32_t addr = mmCRTCV_START_LINE_CONTROL;
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uint32_t value = dm_read_reg(tg->ctx, addr);
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if (enable) {
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if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
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set_reg_field_value(
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value,
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3,
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CRTCV_START_LINE_CONTROL,
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CRTC_ADVANCED_START_LINE_POSITION);
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} else {
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set_reg_field_value(
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value,
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4,
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CRTCV_START_LINE_CONTROL,
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CRTC_ADVANCED_START_LINE_POSITION);
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}
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set_reg_field_value(
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value,
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0,
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CRTCV_START_LINE_CONTROL,
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CRTC_LEGACY_REQUESTOR_EN);
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} else {
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set_reg_field_value(
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value,
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2,
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CRTCV_START_LINE_CONTROL,
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CRTC_ADVANCED_START_LINE_POSITION);
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set_reg_field_value(
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value,
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1,
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CRTCV_START_LINE_CONTROL,
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CRTC_LEGACY_REQUESTOR_EN);
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}
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dm_write_reg(tg->ctx, addr, value);
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}
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static void dce110_timing_generator_v_set_blank(struct timing_generator *tg,
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bool enable_blanking)
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{
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if (enable_blanking)
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dce110_timing_generator_v_blank_crtc(tg);
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else
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dce110_timing_generator_v_unblank_crtc(tg);
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}
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static void dce110_timing_generator_v_program_timing(struct timing_generator *tg,
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const struct dc_crtc_timing *timing,
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bool use_vbios)
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{
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if (use_vbios)
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dce110_timing_generator_program_timing_generator(tg, timing);
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else
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dce110_timing_generator_v_program_blanking(tg, timing);
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}
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static void dce110_timing_generator_v_program_blank_color(
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struct timing_generator *tg,
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const struct tg_color *black_color)
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{
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uint32_t addr = mmCRTCV_BLACK_COLOR;
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uint32_t value = dm_read_reg(tg->ctx, addr);
|
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set_reg_field_value(
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value,
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black_color->color_b_cb,
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CRTCV_BLACK_COLOR,
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CRTC_BLACK_COLOR_B_CB);
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set_reg_field_value(
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value,
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black_color->color_g_y,
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CRTCV_BLACK_COLOR,
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CRTC_BLACK_COLOR_G_Y);
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set_reg_field_value(
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value,
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black_color->color_r_cr,
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CRTCV_BLACK_COLOR,
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CRTC_BLACK_COLOR_R_CR);
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dm_write_reg(tg->ctx, addr, value);
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}
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static void dce110_timing_generator_v_set_overscan_color_black(
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struct timing_generator *tg,
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const struct tg_color *color)
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{
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struct dc_context *ctx = tg->ctx;
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uint32_t addr;
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uint32_t value = 0;
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set_reg_field_value(
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value,
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color->color_b_cb,
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CRTC_OVERSCAN_COLOR,
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CRTC_OVERSCAN_COLOR_BLUE);
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set_reg_field_value(
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value,
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color->color_r_cr,
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CRTC_OVERSCAN_COLOR,
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CRTC_OVERSCAN_COLOR_RED);
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set_reg_field_value(
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value,
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color->color_g_y,
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CRTC_OVERSCAN_COLOR,
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CRTC_OVERSCAN_COLOR_GREEN);
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addr = mmCRTCV_OVERSCAN_COLOR;
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dm_write_reg(ctx, addr, value);
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addr = mmCRTCV_BLACK_COLOR;
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dm_write_reg(ctx, addr, value);
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/* This is desirable to have a constant DAC output voltage during the
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* blank time that is higher than the 0 volt reference level that the
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* DAC outputs when the NBLANK signal
|
* is asserted low, such as for output to an analog TV. */
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addr = mmCRTCV_BLANK_DATA_COLOR;
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dm_write_reg(ctx, addr, value);
|
|
/* TO DO we have to program EXT registers and we need to know LB DATA
|
* format because it is used when more 10 , i.e. 12 bits per color
|
*
|
* m_mmDxCRTC_OVERSCAN_COLOR_EXT
|
* m_mmDxCRTC_BLACK_COLOR_EXT
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* m_mmDxCRTC_BLANK_DATA_COLOR_EXT
|
*/
|
}
|
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static void dce110_tg_v_program_blank_color(struct timing_generator *tg,
|
const struct tg_color *black_color)
|
{
|
uint32_t addr = mmCRTCV_BLACK_COLOR;
|
uint32_t value = dm_read_reg(tg->ctx, addr);
|
|
set_reg_field_value(
|
value,
|
black_color->color_b_cb,
|
CRTCV_BLACK_COLOR,
|
CRTC_BLACK_COLOR_B_CB);
|
set_reg_field_value(
|
value,
|
black_color->color_g_y,
|
CRTCV_BLACK_COLOR,
|
CRTC_BLACK_COLOR_G_Y);
|
set_reg_field_value(
|
value,
|
black_color->color_r_cr,
|
CRTCV_BLACK_COLOR,
|
CRTC_BLACK_COLOR_R_CR);
|
|
dm_write_reg(tg->ctx, addr, value);
|
|
addr = mmCRTCV_BLANK_DATA_COLOR;
|
dm_write_reg(tg->ctx, addr, value);
|
}
|
|
static void dce110_timing_generator_v_set_overscan_color(struct timing_generator *tg,
|
const struct tg_color *overscan_color)
|
{
|
struct dc_context *ctx = tg->ctx;
|
uint32_t value = 0;
|
uint32_t addr;
|
|
set_reg_field_value(
|
value,
|
overscan_color->color_b_cb,
|
CRTCV_OVERSCAN_COLOR,
|
CRTC_OVERSCAN_COLOR_BLUE);
|
|
set_reg_field_value(
|
value,
|
overscan_color->color_g_y,
|
CRTCV_OVERSCAN_COLOR,
|
CRTC_OVERSCAN_COLOR_GREEN);
|
|
set_reg_field_value(
|
value,
|
overscan_color->color_r_cr,
|
CRTCV_OVERSCAN_COLOR,
|
CRTC_OVERSCAN_COLOR_RED);
|
|
addr = mmCRTCV_OVERSCAN_COLOR;
|
dm_write_reg(ctx, addr, value);
|
}
|
|
static void dce110_timing_generator_v_set_colors(struct timing_generator *tg,
|
const struct tg_color *blank_color,
|
const struct tg_color *overscan_color)
|
{
|
if (blank_color != NULL)
|
dce110_tg_v_program_blank_color(tg, blank_color);
|
if (overscan_color != NULL)
|
dce110_timing_generator_v_set_overscan_color(tg, overscan_color);
|
}
|
|
static void dce110_timing_generator_v_set_early_control(
|
struct timing_generator *tg,
|
uint32_t early_cntl)
|
{
|
uint32_t regval;
|
uint32_t address = mmCRTC_CONTROL;
|
|
regval = dm_read_reg(tg->ctx, address);
|
set_reg_field_value(regval, early_cntl,
|
CRTCV_CONTROL, CRTC_HBLANK_EARLY_CONTROL);
|
dm_write_reg(tg->ctx, address, regval);
|
}
|
|
static uint32_t dce110_timing_generator_v_get_vblank_counter(struct timing_generator *tg)
|
{
|
uint32_t addr = mmCRTCV_STATUS_FRAME_COUNT;
|
uint32_t value = dm_read_reg(tg->ctx, addr);
|
uint32_t field = get_reg_field_value(
|
value, CRTCV_STATUS_FRAME_COUNT, CRTC_FRAME_COUNT);
|
|
return field;
|
}
|
|
static bool dce110_timing_generator_v_did_triggered_reset_occur(
|
struct timing_generator *tg)
|
{
|
DC_LOG_ERROR("Timing Sync not supported on underlay pipe\n");
|
return false;
|
}
|
|
static void dce110_timing_generator_v_setup_global_swap_lock(
|
struct timing_generator *tg,
|
const struct dcp_gsl_params *gsl_params)
|
{
|
DC_LOG_ERROR("Timing Sync not supported on underlay pipe\n");
|
return;
|
}
|
|
static void dce110_timing_generator_v_enable_reset_trigger(
|
struct timing_generator *tg,
|
int source_tg_inst)
|
{
|
DC_LOG_ERROR("Timing Sync not supported on underlay pipe\n");
|
return;
|
}
|
|
static void dce110_timing_generator_v_disable_reset_trigger(
|
struct timing_generator *tg)
|
{
|
DC_LOG_ERROR("Timing Sync not supported on underlay pipe\n");
|
return;
|
}
|
|
static void dce110_timing_generator_v_tear_down_global_swap_lock(
|
struct timing_generator *tg)
|
{
|
DC_LOG_ERROR("Timing Sync not supported on underlay pipe\n");
|
return;
|
}
|
|
static void dce110_timing_generator_v_disable_vga(
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struct timing_generator *tg)
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{
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return;
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}
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/** ********************************************************************************************
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*
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* DCE11 Timing Generator Constructor / Destructor
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*
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*********************************************************************************************/
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static const struct timing_generator_funcs dce110_tg_v_funcs = {
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.validate_timing = dce110_tg_validate_timing,
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.program_timing = dce110_timing_generator_v_program_timing,
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.enable_crtc = dce110_timing_generator_v_enable_crtc,
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.disable_crtc = dce110_timing_generator_v_disable_crtc,
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.is_counter_moving = dce110_timing_generator_v_is_counter_moving,
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.get_position = NULL, /* Not to be implemented for underlay*/
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.get_frame_count = dce110_timing_generator_v_get_vblank_counter,
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.set_early_control = dce110_timing_generator_v_set_early_control,
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.wait_for_state = dce110_timing_generator_v_wait_for_state,
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.set_blank = dce110_timing_generator_v_set_blank,
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.set_colors = dce110_timing_generator_v_set_colors,
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.set_overscan_blank_color =
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dce110_timing_generator_v_set_overscan_color_black,
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.set_blank_color = dce110_timing_generator_v_program_blank_color,
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.disable_vga = dce110_timing_generator_v_disable_vga,
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.did_triggered_reset_occur =
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dce110_timing_generator_v_did_triggered_reset_occur,
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.setup_global_swap_lock =
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dce110_timing_generator_v_setup_global_swap_lock,
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.enable_reset_trigger = dce110_timing_generator_v_enable_reset_trigger,
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.disable_reset_trigger = dce110_timing_generator_v_disable_reset_trigger,
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.tear_down_global_swap_lock =
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dce110_timing_generator_v_tear_down_global_swap_lock,
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.enable_advanced_request =
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dce110_timing_generator_v_enable_advanced_request
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};
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void dce110_timing_generator_v_construct(
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struct dce110_timing_generator *tg110,
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struct dc_context *ctx)
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{
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tg110->controller_id = CONTROLLER_ID_UNDERLAY0;
|
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tg110->base.funcs = &dce110_tg_v_funcs;
|
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tg110->base.ctx = ctx;
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tg110->base.bp = ctx->dc_bios;
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tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
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tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
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tg110->min_h_blank = 56;
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tg110->min_h_front_porch = 4;
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tg110->min_h_back_porch = 4;
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}
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