//
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// Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions
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//
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// Copyright (C) 2016 Linaro Ltd <ard.biesheuvel@linaro.org>
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License version 2 as
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// published by the Free Software Foundation.
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//
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//
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// Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
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//
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// Copyright (c) 2013, Intel Corporation
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//
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// Authors:
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// Erdinc Ozturk <erdinc.ozturk@intel.com>
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// Vinodh Gopal <vinodh.gopal@intel.com>
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// James Guilford <james.guilford@intel.com>
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// Tim Chen <tim.c.chen@linux.intel.com>
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//
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// This software is available to you under a choice of one of two
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// licenses. You may choose to be licensed under the terms of the GNU
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// General Public License (GPL) Version 2, available from the file
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// COPYING in the main directory of this source tree, or the
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// OpenIB.org BSD license below:
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// * Neither the name of the Intel Corporation nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION ""AS IS"" AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Function API:
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// UINT16 crc_t10dif_pcl(
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// UINT16 init_crc, //initial CRC value, 16 bits
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// const unsigned char *buf, //buffer pointer to calculate CRC on
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// UINT64 len //buffer length in bytes (64-bit data)
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// );
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//
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// Reference paper titled "Fast CRC Computation for Generic
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// Polynomials Using PCLMULQDQ Instruction"
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// URL: http://www.intel.com/content/dam/www/public/us/en/documents
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// /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
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//
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//
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#ifdef CONFIG_CPU_ENDIAN_BE8
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#define CPU_LE(code...)
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#else
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#define CPU_LE(code...) code
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#endif
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.text
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.fpu crypto-neon-fp-armv8
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arg1_low32 .req r0
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arg2 .req r1
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arg3 .req r2
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qzr .req q13
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q0l .req d0
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q0h .req d1
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q1l .req d2
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q1h .req d3
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q2l .req d4
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q2h .req d5
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q3l .req d6
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q3h .req d7
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q4l .req d8
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q4h .req d9
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q5l .req d10
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q5h .req d11
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q6l .req d12
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q6h .req d13
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q7l .req d14
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q7h .req d15
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ENTRY(crc_t10dif_pmull)
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vmov.i8 qzr, #0 // init zero register
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// adjust the 16-bit initial_crc value, scale it to 32 bits
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lsl arg1_low32, arg1_low32, #16
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// check if smaller than 256
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cmp arg3, #256
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// for sizes less than 128, we can't fold 64B at a time...
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blt _less_than_128
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// load the initial crc value
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// crc value does not need to be byte-reflected, but it needs
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// to be moved to the high part of the register.
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// because data will be byte-reflected and will align with
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// initial crc at correct place.
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vmov s0, arg1_low32 // initial crc
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vext.8 q10, qzr, q0, #4
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// receive the initial 64B data, xor the initial crc value
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vld1.64 {q0-q1}, [arg2]!
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vld1.64 {q2-q3}, [arg2]!
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vld1.64 {q4-q5}, [arg2]!
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vld1.64 {q6-q7}, [arg2]!
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CPU_LE( vrev64.8 q0, q0 )
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CPU_LE( vrev64.8 q1, q1 )
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CPU_LE( vrev64.8 q2, q2 )
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CPU_LE( vrev64.8 q3, q3 )
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CPU_LE( vrev64.8 q4, q4 )
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CPU_LE( vrev64.8 q5, q5 )
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CPU_LE( vrev64.8 q6, q6 )
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CPU_LE( vrev64.8 q7, q7 )
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vswp d0, d1
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vswp d2, d3
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vswp d4, d5
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vswp d6, d7
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vswp d8, d9
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vswp d10, d11
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vswp d12, d13
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vswp d14, d15
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// XOR the initial_crc value
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veor.8 q0, q0, q10
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adr ip, rk3
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vld1.64 {q10}, [ip, :128] // xmm10 has rk3 and rk4
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//
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// we subtract 256 instead of 128 to save one instruction from the loop
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//
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sub arg3, arg3, #256
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// at this section of the code, there is 64*x+y (0<=y<64) bytes of
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// buffer. The _fold_64_B_loop will fold 64B at a time
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// until we have 64+y Bytes of buffer
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// fold 64B at a time. This section of the code folds 4 vector
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// registers in parallel
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_fold_64_B_loop:
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.macro fold64, reg1, reg2
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vld1.64 {q11-q12}, [arg2]!
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vmull.p64 q8, \reg1\()h, d21
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vmull.p64 \reg1, \reg1\()l, d20
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vmull.p64 q9, \reg2\()h, d21
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vmull.p64 \reg2, \reg2\()l, d20
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CPU_LE( vrev64.8 q11, q11 )
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CPU_LE( vrev64.8 q12, q12 )
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vswp d22, d23
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vswp d24, d25
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veor.8 \reg1, \reg1, q8
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veor.8 \reg2, \reg2, q9
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veor.8 \reg1, \reg1, q11
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veor.8 \reg2, \reg2, q12
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.endm
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fold64 q0, q1
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fold64 q2, q3
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fold64 q4, q5
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fold64 q6, q7
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subs arg3, arg3, #128
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// check if there is another 64B in the buffer to be able to fold
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bge _fold_64_B_loop
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// at this point, the buffer pointer is pointing at the last y Bytes
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// of the buffer the 64B of folded data is in 4 of the vector
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// registers: v0, v1, v2, v3
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// fold the 8 vector registers to 1 vector register with different
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// constants
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adr ip, rk9
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vld1.64 {q10}, [ip, :128]!
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.macro fold16, reg, rk
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vmull.p64 q8, \reg\()l, d20
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vmull.p64 \reg, \reg\()h, d21
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.ifnb \rk
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vld1.64 {q10}, [ip, :128]!
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.endif
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veor.8 q7, q7, q8
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veor.8 q7, q7, \reg
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.endm
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fold16 q0, rk11
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fold16 q1, rk13
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fold16 q2, rk15
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fold16 q3, rk17
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fold16 q4, rk19
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fold16 q5, rk1
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fold16 q6
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// instead of 64, we add 48 to the loop counter to save 1 instruction
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// from the loop instead of a cmp instruction, we use the negative
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// flag with the jl instruction
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adds arg3, arg3, #(128-16)
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blt _final_reduction_for_128
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// now we have 16+y bytes left to reduce. 16 Bytes is in register v7
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// and the rest is in memory. We can fold 16 bytes at a time if y>=16
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// continue folding 16B at a time
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_16B_reduction_loop:
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vmull.p64 q8, d14, d20
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vmull.p64 q7, d15, d21
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veor.8 q7, q7, q8
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vld1.64 {q0}, [arg2]!
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CPU_LE( vrev64.8 q0, q0 )
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vswp d0, d1
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veor.8 q7, q7, q0
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subs arg3, arg3, #16
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// instead of a cmp instruction, we utilize the flags with the
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// jge instruction equivalent of: cmp arg3, 16-16
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// check if there is any more 16B in the buffer to be able to fold
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bge _16B_reduction_loop
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// now we have 16+z bytes left to reduce, where 0<= z < 16.
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// first, we reduce the data in the xmm7 register
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_final_reduction_for_128:
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// check if any more data to fold. If not, compute the CRC of
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// the final 128 bits
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adds arg3, arg3, #16
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beq _128_done
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// here we are getting data that is less than 16 bytes.
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// since we know that there was data before the pointer, we can
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// offset the input pointer before the actual point, to receive
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// exactly 16 bytes. after that the registers need to be adjusted.
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_get_last_two_regs:
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add arg2, arg2, arg3
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sub arg2, arg2, #16
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vld1.64 {q1}, [arg2]
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CPU_LE( vrev64.8 q1, q1 )
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vswp d2, d3
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// get rid of the extra data that was loaded before
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// load the shift constant
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adr ip, tbl_shf_table + 16
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sub ip, ip, arg3
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vld1.8 {q0}, [ip]
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// shift v2 to the left by arg3 bytes
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vtbl.8 d4, {d14-d15}, d0
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vtbl.8 d5, {d14-d15}, d1
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// shift v7 to the right by 16-arg3 bytes
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vmov.i8 q9, #0x80
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veor.8 q0, q0, q9
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vtbl.8 d18, {d14-d15}, d0
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vtbl.8 d19, {d14-d15}, d1
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// blend
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vshr.s8 q0, q0, #7 // convert to 8-bit mask
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vbsl.8 q0, q2, q1
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// fold 16 Bytes
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vmull.p64 q8, d18, d20
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vmull.p64 q7, d19, d21
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veor.8 q7, q7, q8
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veor.8 q7, q7, q0
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_128_done:
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// compute crc of a 128-bit value
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vldr d20, rk5
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vldr d21, rk6 // rk5 and rk6 in xmm10
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// 64b fold
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vext.8 q0, qzr, q7, #8
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vmull.p64 q7, d15, d20
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veor.8 q7, q7, q0
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// 32b fold
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vext.8 q0, q7, qzr, #12
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vmov s31, s3
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vmull.p64 q0, d0, d21
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veor.8 q7, q0, q7
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// barrett reduction
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_barrett:
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vldr d20, rk7
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vldr d21, rk8
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vmull.p64 q0, d15, d20
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vext.8 q0, qzr, q0, #12
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vmull.p64 q0, d1, d21
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vext.8 q0, qzr, q0, #12
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veor.8 q7, q7, q0
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vmov r0, s29
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_cleanup:
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// scale the result back to 16 bits
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lsr r0, r0, #16
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bx lr
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_less_than_128:
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teq arg3, #0
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beq _cleanup
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vmov.i8 q0, #0
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vmov s3, arg1_low32 // get the initial crc value
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vld1.64 {q7}, [arg2]!
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CPU_LE( vrev64.8 q7, q7 )
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vswp d14, d15
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veor.8 q7, q7, q0
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cmp arg3, #16
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beq _128_done // exactly 16 left
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blt _less_than_16_left
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// now if there is, load the constants
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vldr d20, rk1
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vldr d21, rk2 // rk1 and rk2 in xmm10
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// check if there is enough buffer to be able to fold 16B at a time
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subs arg3, arg3, #32
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addlt arg3, arg3, #16
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blt _get_last_two_regs
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b _16B_reduction_loop
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_less_than_16_left:
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// shl r9, 4
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adr ip, tbl_shf_table + 16
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sub ip, ip, arg3
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vld1.8 {q0}, [ip]
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vmov.i8 q9, #0x80
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veor.8 q0, q0, q9
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vtbl.8 d18, {d14-d15}, d0
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vtbl.8 d15, {d14-d15}, d1
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vmov d14, d18
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b _128_done
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ENDPROC(crc_t10dif_pmull)
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// precomputed constants
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// these constants are precomputed from the poly:
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// 0x8bb70000 (0x8bb7 scaled to 32 bits)
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.align 4
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// Q = 0x18BB70000
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// rk1 = 2^(32*3) mod Q << 32
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// rk2 = 2^(32*5) mod Q << 32
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// rk3 = 2^(32*15) mod Q << 32
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// rk4 = 2^(32*17) mod Q << 32
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// rk5 = 2^(32*3) mod Q << 32
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// rk6 = 2^(32*2) mod Q << 32
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// rk7 = floor(2^64/Q)
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// rk8 = Q
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rk3: .quad 0x9d9d000000000000
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rk4: .quad 0x7cf5000000000000
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rk5: .quad 0x2d56000000000000
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rk6: .quad 0x1368000000000000
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rk7: .quad 0x00000001f65a57f8
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rk8: .quad 0x000000018bb70000
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rk9: .quad 0xceae000000000000
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rk10: .quad 0xbfd6000000000000
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rk11: .quad 0x1e16000000000000
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rk12: .quad 0x713c000000000000
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rk13: .quad 0xf7f9000000000000
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rk14: .quad 0x80a6000000000000
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rk15: .quad 0x044c000000000000
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rk16: .quad 0xe658000000000000
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rk17: .quad 0xad18000000000000
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rk18: .quad 0xa497000000000000
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rk19: .quad 0x6ee3000000000000
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rk20: .quad 0xe7b5000000000000
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rk1: .quad 0x2d56000000000000
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rk2: .quad 0x06df000000000000
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tbl_shf_table:
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// use these values for shift constants for the tbl/tbx instruction
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// different alignments result in values as shown:
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// DDQ 0x008f8e8d8c8b8a898887868584838281 # shl 15 (16-1) / shr1
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// DDQ 0x01008f8e8d8c8b8a8988878685848382 # shl 14 (16-3) / shr2
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// DDQ 0x0201008f8e8d8c8b8a89888786858483 # shl 13 (16-4) / shr3
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// DDQ 0x030201008f8e8d8c8b8a898887868584 # shl 12 (16-4) / shr4
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// DDQ 0x04030201008f8e8d8c8b8a8988878685 # shl 11 (16-5) / shr5
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// DDQ 0x0504030201008f8e8d8c8b8a89888786 # shl 10 (16-6) / shr6
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// DDQ 0x060504030201008f8e8d8c8b8a898887 # shl 9 (16-7) / shr7
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// DDQ 0x07060504030201008f8e8d8c8b8a8988 # shl 8 (16-8) / shr8
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// DDQ 0x0807060504030201008f8e8d8c8b8a89 # shl 7 (16-9) / shr9
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// DDQ 0x090807060504030201008f8e8d8c8b8a # shl 6 (16-10) / shr10
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// DDQ 0x0a090807060504030201008f8e8d8c8b # shl 5 (16-11) / shr11
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// DDQ 0x0b0a090807060504030201008f8e8d8c # shl 4 (16-12) / shr12
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// DDQ 0x0c0b0a090807060504030201008f8e8d # shl 3 (16-13) / shr13
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// DDQ 0x0d0c0b0a090807060504030201008f8e # shl 2 (16-14) / shr14
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// DDQ 0x0e0d0c0b0a090807060504030201008f # shl 1 (16-15) / shr15
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.byte 0x0, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87
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.byte 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f
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.byte 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
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.byte 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe , 0x0
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