From 90b202b59fa2bdb68314a23471b32d3e16602bc8 Mon Sep 17 00:00:00 2001
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From: Stafford Horne <shorne@gmail.com>
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Date: Sun, 2 May 2021 06:11:44 +0900
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Subject: [PATCH] or1k: Add mcmodel option to handle large GOTs
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When building libgeos we get an error with:
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linux-uclibc/9.3.0/crtbeginS.o: in function `__do_global_dtors_aux':
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crtstuff.c:(.text+0x118): relocation truncated to fit: R_OR1K_GOT16 against symbol `__cxa_finalize' defined in .text section in
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/home/shorne/work/openrisc/3eb9f9d0f6d8274b2d19753c006bd83f7d536e3c/output/host/or1k-buildroot-linux-uclibc/sysroot/lib/libc.so.
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This is caused by GOT code having a limit of 64k. In OpenRISC this
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looks to be the only relocation code pattern to be limited to 64k.
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This patch allows specifying a new option -mcmodel=large which can be
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used to generate 2 more instructions to construct 32-bit addresses for
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up to 4G GOTs.
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gcc/ChangeLog:
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PR 99783
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* config/or1k/or1k-opts.h: New file.
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* config/or1k/or1k.c (or1k_legitimize_address_1, print_reloc):
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Support generating gotha relocations if -mcmodel=large is
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specified.
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* config/or1k/or1k.h (TARGET_CMODEL_SMALL, TARGET_CMODEL_LARGE):
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New macros.
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* config/or1k/or1k.opt (mcmodel=): New option.
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* doc/invoke.text (OpenRISC Options): Document mcmodel.
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Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
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---
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gcc/config/or1k/or1k-opts.h | 30 ++++++++++++++++++++++++++++++
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gcc/config/or1k/or1k.c | 11 +++++++++--
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gcc/config/or1k/or1k.h | 7 +++++++
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gcc/config/or1k/or1k.opt | 19 +++++++++++++++++++
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gcc/doc/invoke.texi | 13 ++++++++++++-
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5 files changed, 77 insertions(+), 3 deletions(-)
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create mode 100644 gcc/config/or1k/or1k-opts.h
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diff --git a/gcc/config/or1k/or1k-opts.h b/gcc/config/or1k/or1k-opts.h
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new file mode 100644
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index 00000000000..f791b894fdd
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--- /dev/null
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+++ b/gcc/config/or1k/or1k-opts.h
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@@ -0,0 +1,30 @@
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+/* Definitions for option handling for OpenRISC.
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+ Copyright (C) 2021 Free Software Foundation, Inc.
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+ Contributed by Stafford Horne.
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+
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+ This file is part of GCC.
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+
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+ GCC is free software; you can redistribute it and/or modify it
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+ under the terms of the GNU General Public License as published
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+ by the Free Software Foundation; either version 3, or (at your
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+ option) any later version.
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+
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+ GCC is distributed in the hope that it will be useful, but WITHOUT
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+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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+ License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with GCC; see the file COPYING3. If not see
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+ <http://www.gnu.org/licenses/>. */
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+
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+#ifndef GCC_OR1K_OPTS_H
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+#define GCC_OR1K_OPTS_H
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+
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+/* The OpenRISC code generation models available. */
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+enum or1k_cmodel_type {
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+ CMODEL_SMALL,
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+ CMODEL_LARGE
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+};
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+
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+#endif /* GCC_OR1K_OPTS_H */
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diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
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index fc10fcfabde..df67d72b139 100644
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--- a/gcc/config/or1k/or1k.c
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+++ b/gcc/config/or1k/or1k.c
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@@ -750,7 +750,14 @@ or1k_legitimize_address_1 (rtx x, rtx scratch)
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{
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base = gen_sym_unspec (base, UNSPEC_GOT);
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crtl->uses_pic_offset_table = 1;
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- t2 = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, base);
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+ if (TARGET_CMODEL_LARGE)
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+ {
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+ emit_insn (gen_rtx_SET (t1, gen_rtx_HIGH (Pmode, base)));
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+ emit_insn (gen_add3_insn (t1, t1, pic_offset_table_rtx));
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+ t2 = gen_rtx_LO_SUM (Pmode, t1, base);
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+ }
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+ else
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+ t2 = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, base);
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t2 = gen_const_mem (Pmode, t2);
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emit_insn (gen_rtx_SET (t1, t2));
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base = t1;
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@@ -1097,7 +1104,7 @@ print_reloc (FILE *stream, rtx x, HOST_WIDE_INT add, reloc_kind kind)
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no special markup. */
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static const char * const relocs[RKIND_MAX][RTYPE_MAX] = {
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{ "lo", "got", "gotofflo", "tpofflo", "gottpofflo", "tlsgdlo" },
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- { "ha", NULL, "gotoffha", "tpoffha", "gottpoffha", "tlsgdhi" },
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+ { "ha", "gotha", "gotoffha", "tpoffha", "gottpoffha", "tlsgdhi" },
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};
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reloc_type type = RTYPE_DIRECT;
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diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
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index feee702d89c..dbaf0d0fe4c 100644
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--- a/gcc/config/or1k/or1k.h
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+++ b/gcc/config/or1k/or1k.h
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@@ -21,6 +21,8 @@
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#ifndef GCC_OR1K_H
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#define GCC_OR1K_H
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+#include "config/or1k/or1k-opts.h"
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+
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/* Names to predefine in the preprocessor for this target machine. */
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#define TARGET_CPU_CPP_BUILTINS() \
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do \
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@@ -35,6 +37,11 @@
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} \
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while (0)
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+#define TARGET_CMODEL_SMALL \
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+ (or1k_code_model == CMODEL_SMALL)
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+#define TARGET_CMODEL_LARGE \
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+ (or1k_code_model == CMODEL_LARGE)
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+
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/* Storage layout. */
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#define DEFAULT_SIGNED_CHAR 1
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diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or1k.opt
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index 7bdbd842dd4..116524c3441 100644
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--- a/gcc/config/or1k/or1k.opt
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+++ b/gcc/config/or1k/or1k.opt
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@@ -23,6 +23,9 @@
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; Please try to keep this file in ASCII collating order.
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+HeaderInclude
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+config/or1k/or1k-opts.h
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+
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mhard-div
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Target RejectNegative InverseMask(SOFT_DIV)
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Use hardware divide instructions, use -msoft-div for emulation.
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@@ -31,6 +34,22 @@ mhard-mul
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Target RejectNegative InverseMask(SOFT_MUL).
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Use hardware multiply instructions, use -msoft-mul for emulation.
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+mcmodel=
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+Target RejectNegative Joined Enum(or1k_cmodel_type) Var(or1k_code_model) Init(CMODEL_SMALL)
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+Specify the code model used for accessing memory addresses. Specifying large
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+enables generating binaries with large global offset tables. By default the
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+value is small.
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+
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+Enum
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+Name(or1k_cmodel_type) Type(enum or1k_cmodel_type)
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+Known code model types (for use with the -mcmodel= option):
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+
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+EnumValue
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+Enum(or1k_cmodel_type) String(small) Value(CMODEL_SMALL)
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+
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+EnumValue
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+Enum(or1k_cmodel_type) String(large) Value(CMODEL_LARGE)
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+
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mcmov
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Target RejectNegative Mask(CMOV)
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Allows generation of binaries which use the l.cmov instruction. If your target
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diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
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index 7b5f6e03d9f..683c64417af 100644
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--- a/gcc/doc/invoke.texi
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+++ b/gcc/doc/invoke.texi
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@@ -1032,7 +1032,9 @@ Objective-C and Objective-C++ Dialects}.
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@emph{OpenRISC Options}
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@gccoptlist{-mboard=@var{name} -mnewlib -mhard-mul -mhard-div @gol
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-msoft-mul -msoft-div @gol
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--mcmov -mror -msext -msfimm -mshftimm}
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+-mcmov -mror -mrori -msext -msfimm -mshftimm @gol
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+-mcmodel=@var{code-model}}
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+
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@emph{PDP-11 Options}
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@gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol
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@@ -27462,6 +27464,15 @@ MWAITX, SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,
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SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit
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instruction set extensions.)
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+@item -mcmodel=small
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+@opindex mcmodel=small
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+Generate OpenRISC code for the small model: The GOT is limited to 64k. This is
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+the default model.
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+
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+@item -mcmodel=large
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+@opindex mcmodel=large
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+Generate OpenRISC code for the large model: The GOT may grow up to 4G in size.
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+
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@item btver1
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CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This
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--
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2.31.1
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