/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _CI_SMUMANAGER_H_
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#define _CI_SMUMANAGER_H_
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#define SMU__NUM_SCLK_DPM_STATE 8
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#define SMU__NUM_MCLK_DPM_LEVELS 6
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#define SMU__NUM_LCLK_DPM_LEVELS 8
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#define SMU__NUM_PCIE_DPM_LEVELS 8
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#include "smu7_discrete.h"
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#include <pp_endian.h>
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#include "ppatomctrl.h"
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struct ci_pt_defaults {
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u8 svi_load_line_en;
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u8 svi_load_line_vddc;
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u8 tdc_vddc_throttle_release_limit_perc;
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u8 tdc_mawt;
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u8 tdc_waterfall_ctl;
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u8 dte_ambient_temp_base;
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u32 display_cac;
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u32 bapm_temp_gradient;
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u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
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u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
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};
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struct ci_mc_reg_entry {
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uint32_t mclk_max;
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uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
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};
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struct ci_mc_reg_table {
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uint8_t last;
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uint8_t num_entries;
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uint16_t validflag;
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struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
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SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
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};
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struct ci_smumgr {
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uint32_t soft_regs_start;
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uint32_t dpm_table_start;
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uint32_t mc_reg_table_start;
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uint32_t fan_table_start;
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uint32_t arb_table_start;
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uint32_t ulv_setting_starts;
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struct SMU7_Discrete_DpmTable smc_state_table;
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struct SMU7_Discrete_PmFuses power_tune_table;
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const struct ci_pt_defaults *power_tune_defaults;
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SMU7_Discrete_MCRegisters mc_regs;
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struct ci_mc_reg_table mc_reg_table;
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};
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#endif
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