/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU10_DRIVER_IF_H
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#define SMU10_DRIVER_IF_H
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#define SMU10_DRIVER_IF_VERSION 0x6
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#define NUM_DSPCLK_LEVELS 8
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typedef struct {
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int32_t value;
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uint32_t numFractionalBits;
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} FloatInIntFormat_t;
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typedef enum {
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DSPCLK_DCEFCLK = 0,
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DSPCLK_DISPCLK,
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DSPCLK_PIXCLK,
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DSPCLK_PHYCLK,
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DSPCLK_COUNT,
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} DSPCLK_e;
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typedef struct {
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uint16_t Freq;
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uint16_t Vid;
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} DisplayClockTable_t;
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typedef struct {
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uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */
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uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */
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uint16_t MinMclk;
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uint16_t MaxMclk;
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uint8_t WmSetting;
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uint8_t Padding[3];
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} WatermarkRowGeneric_t;
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#define NUM_WM_RANGES 4
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typedef enum {
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WM_SOCCLK = 0,
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WM_DCFCLK,
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WM_COUNT,
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} WM_CLOCK_e;
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typedef struct {
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WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
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uint32_t MmHubPadding[7];
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} Watermarks_t;
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typedef enum {
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CUSTOM_DPM_SETTING_GFXCLK,
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CUSTOM_DPM_SETTING_CCLK,
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CUSTOM_DPM_SETTING_FCLK_CCX,
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CUSTOM_DPM_SETTING_FCLK_GFX,
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CUSTOM_DPM_SETTING_FCLK_STALLS,
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CUSTOM_DPM_SETTING_LCLK,
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CUSTOM_DPM_SETTING_COUNT,
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} CUSTOM_DPM_SETTING_e;
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typedef struct {
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uint8_t ActiveHystLimit;
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uint8_t IdleHystLimit;
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uint8_t FPS;
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uint8_t MinActiveFreqType;
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FloatInIntFormat_t MinActiveFreq;
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FloatInIntFormat_t PD_Data_limit;
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FloatInIntFormat_t PD_Data_time_constant;
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FloatInIntFormat_t PD_Data_error_coeff;
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FloatInIntFormat_t PD_Data_error_rate_coeff;
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} DpmActivityMonitorCoeffExt_t;
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typedef struct {
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DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
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} CustomDpmSettings_t;
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#define NUM_SOCCLK_DPM_LEVELS 8
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#define NUM_DCEFCLK_DPM_LEVELS 4
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#define NUM_FCLK_DPM_LEVELS 4
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#define NUM_MEMCLK_DPM_LEVELS 4
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typedef struct {
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uint32_t Freq; /* In MHz */
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uint32_t Vol; /* Millivolts with 2 fractional bits */
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} DpmClock_t;
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typedef struct {
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DpmClock_t DcefClocks[NUM_DCEFCLK_DPM_LEVELS];
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DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
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DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
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DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS];
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} DpmClocks_t;
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#endif
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