/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*/
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#include <linux/string.h>
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#include <linux/acpi.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/amdgpu_drm.h>
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#include "dm_services.h"
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#include "amdgpu.h"
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#include "amdgpu_dm.h"
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#include "amdgpu_dm_irq.h"
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#include "amdgpu_pm.h"
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#include "dm_pp_smu.h"
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bool dm_pp_apply_display_requirements(
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const struct dc_context *ctx,
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const struct dm_pp_display_configuration *pp_display_cfg)
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{
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struct amdgpu_device *adev = ctx->driver_context;
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int i;
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if (adev->pm.dpm_enabled) {
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memset(&adev->pm.pm_display_cfg, 0,
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sizeof(adev->pm.pm_display_cfg));
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adev->pm.pm_display_cfg.cpu_cc6_disable =
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pp_display_cfg->cpu_cc6_disable;
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adev->pm.pm_display_cfg.cpu_pstate_disable =
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pp_display_cfg->cpu_pstate_disable;
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adev->pm.pm_display_cfg.cpu_pstate_separation_time =
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pp_display_cfg->cpu_pstate_separation_time;
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adev->pm.pm_display_cfg.nb_pstate_switch_disable =
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pp_display_cfg->nb_pstate_switch_disable;
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adev->pm.pm_display_cfg.num_display =
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pp_display_cfg->display_count;
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adev->pm.pm_display_cfg.num_path_including_non_display =
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pp_display_cfg->display_count;
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adev->pm.pm_display_cfg.min_core_set_clock =
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pp_display_cfg->min_engine_clock_khz/10;
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adev->pm.pm_display_cfg.min_core_set_clock_in_sr =
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pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
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adev->pm.pm_display_cfg.min_mem_set_clock =
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pp_display_cfg->min_memory_clock_khz/10;
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adev->pm.pm_display_cfg.min_dcef_deep_sleep_set_clk =
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pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
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adev->pm.pm_display_cfg.min_dcef_set_clk =
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pp_display_cfg->min_dcfclock_khz/10;
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adev->pm.pm_display_cfg.multi_monitor_in_sync =
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pp_display_cfg->all_displays_in_sync;
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adev->pm.pm_display_cfg.min_vblank_time =
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pp_display_cfg->avail_mclk_switch_time_us;
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adev->pm.pm_display_cfg.display_clk =
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pp_display_cfg->disp_clk_khz/10;
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adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency =
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pp_display_cfg->avail_mclk_switch_time_in_disp_active_us;
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adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index;
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adev->pm.pm_display_cfg.line_time_in_us =
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pp_display_cfg->line_time_in_us;
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adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh;
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adev->pm.pm_display_cfg.crossfire_display_index = -1;
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adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
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for (i = 0; i < pp_display_cfg->display_count; i++) {
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const struct dm_pp_single_disp_config *dc_cfg =
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&pp_display_cfg->disp_configs[i];
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adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1;
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}
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/* TODO: complete implementation of
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* pp_display_configuration_change().
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* Follow example of:
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* PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c
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* PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */
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if (adev->powerplay.pp_funcs->display_configuration_change)
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adev->powerplay.pp_funcs->display_configuration_change(
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adev->powerplay.pp_handle,
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&adev->pm.pm_display_cfg);
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/* TODO: replace by a separate call to 'apply display cfg'? */
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amdgpu_pm_compute_clocks(adev);
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}
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return true;
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}
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static void get_default_clock_levels(
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enum dm_pp_clock_type clk_type,
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struct dm_pp_clock_levels *clks)
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{
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uint32_t disp_clks_in_khz[6] = {
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300000, 400000, 496560, 626090, 685720, 757900 };
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uint32_t sclks_in_khz[6] = {
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300000, 360000, 423530, 514290, 626090, 720000 };
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uint32_t mclks_in_khz[2] = { 333000, 800000 };
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switch (clk_type) {
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case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
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clks->num_levels = 6;
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memmove(clks->clocks_in_khz, disp_clks_in_khz,
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sizeof(disp_clks_in_khz));
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break;
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case DM_PP_CLOCK_TYPE_ENGINE_CLK:
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clks->num_levels = 6;
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memmove(clks->clocks_in_khz, sclks_in_khz,
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sizeof(sclks_in_khz));
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break;
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case DM_PP_CLOCK_TYPE_MEMORY_CLK:
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clks->num_levels = 2;
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memmove(clks->clocks_in_khz, mclks_in_khz,
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sizeof(mclks_in_khz));
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break;
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default:
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clks->num_levels = 0;
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break;
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}
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}
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static enum amd_pp_clock_type dc_to_pp_clock_type(
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enum dm_pp_clock_type dm_pp_clk_type)
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{
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enum amd_pp_clock_type amd_pp_clk_type = 0;
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switch (dm_pp_clk_type) {
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case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
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amd_pp_clk_type = amd_pp_disp_clock;
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break;
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case DM_PP_CLOCK_TYPE_ENGINE_CLK:
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amd_pp_clk_type = amd_pp_sys_clock;
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break;
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case DM_PP_CLOCK_TYPE_MEMORY_CLK:
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amd_pp_clk_type = amd_pp_mem_clock;
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break;
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case DM_PP_CLOCK_TYPE_DCEFCLK:
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amd_pp_clk_type = amd_pp_dcef_clock;
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break;
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case DM_PP_CLOCK_TYPE_DCFCLK:
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amd_pp_clk_type = amd_pp_dcf_clock;
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break;
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case DM_PP_CLOCK_TYPE_PIXELCLK:
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amd_pp_clk_type = amd_pp_pixel_clock;
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break;
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case DM_PP_CLOCK_TYPE_FCLK:
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amd_pp_clk_type = amd_pp_f_clock;
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break;
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case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
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amd_pp_clk_type = amd_pp_phy_clock;
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break;
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case DM_PP_CLOCK_TYPE_DPPCLK:
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amd_pp_clk_type = amd_pp_dpp_clock;
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break;
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default:
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DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
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dm_pp_clk_type);
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break;
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}
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return amd_pp_clk_type;
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}
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static enum dm_pp_clocks_state pp_to_dc_powerlevel_state(
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enum PP_DAL_POWERLEVEL max_clocks_state)
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{
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switch (max_clocks_state) {
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case PP_DAL_POWERLEVEL_0:
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return DM_PP_CLOCKS_DPM_STATE_LEVEL_0;
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case PP_DAL_POWERLEVEL_1:
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return DM_PP_CLOCKS_DPM_STATE_LEVEL_1;
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case PP_DAL_POWERLEVEL_2:
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return DM_PP_CLOCKS_DPM_STATE_LEVEL_2;
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case PP_DAL_POWERLEVEL_3:
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return DM_PP_CLOCKS_DPM_STATE_LEVEL_3;
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case PP_DAL_POWERLEVEL_4:
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return DM_PP_CLOCKS_DPM_STATE_LEVEL_4;
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case PP_DAL_POWERLEVEL_5:
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return DM_PP_CLOCKS_DPM_STATE_LEVEL_5;
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case PP_DAL_POWERLEVEL_6:
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return DM_PP_CLOCKS_DPM_STATE_LEVEL_6;
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case PP_DAL_POWERLEVEL_7:
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return DM_PP_CLOCKS_DPM_STATE_LEVEL_7;
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default:
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DRM_ERROR("DM_PPLIB: invalid powerlevel state: %d!\n",
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max_clocks_state);
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return DM_PP_CLOCKS_STATE_INVALID;
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}
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}
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static void pp_to_dc_clock_levels(
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const struct amd_pp_clocks *pp_clks,
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struct dm_pp_clock_levels *dc_clks,
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enum dm_pp_clock_type dc_clk_type)
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{
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uint32_t i;
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if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
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DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
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DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
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pp_clks->count,
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DM_PP_MAX_CLOCK_LEVELS);
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dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
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} else
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dc_clks->num_levels = pp_clks->count;
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DRM_INFO("DM_PPLIB: values for %s clock\n",
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DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
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for (i = 0; i < dc_clks->num_levels; i++) {
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DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
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dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
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}
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}
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static void pp_to_dc_clock_levels_with_latency(
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const struct pp_clock_levels_with_latency *pp_clks,
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struct dm_pp_clock_levels_with_latency *clk_level_info,
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enum dm_pp_clock_type dc_clk_type)
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{
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uint32_t i;
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if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
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DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
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DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
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pp_clks->num_levels,
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DM_PP_MAX_CLOCK_LEVELS);
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clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
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} else
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clk_level_info->num_levels = pp_clks->num_levels;
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DRM_DEBUG("DM_PPLIB: values for %s clock\n",
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DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
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for (i = 0; i < clk_level_info->num_levels; i++) {
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DRM_DEBUG("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
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clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
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clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
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}
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}
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static void pp_to_dc_clock_levels_with_voltage(
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const struct pp_clock_levels_with_voltage *pp_clks,
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struct dm_pp_clock_levels_with_voltage *clk_level_info,
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enum dm_pp_clock_type dc_clk_type)
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{
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uint32_t i;
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if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
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DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
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DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
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pp_clks->num_levels,
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DM_PP_MAX_CLOCK_LEVELS);
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clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
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} else
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clk_level_info->num_levels = pp_clks->num_levels;
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DRM_INFO("DM_PPLIB: values for %s clock\n",
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DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
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for (i = 0; i < clk_level_info->num_levels; i++) {
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DRM_INFO("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
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clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
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clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
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}
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}
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bool dm_pp_get_clock_levels_by_type(
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const struct dc_context *ctx,
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enum dm_pp_clock_type clk_type,
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struct dm_pp_clock_levels *dc_clks)
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{
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struct amdgpu_device *adev = ctx->driver_context;
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void *pp_handle = adev->powerplay.pp_handle;
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struct amd_pp_clocks pp_clks = { 0 };
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struct amd_pp_simple_clock_info validation_clks = { 0 };
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uint32_t i;
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if (adev->powerplay.pp_funcs->get_clock_by_type) {
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if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
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dc_to_pp_clock_type(clk_type), &pp_clks)) {
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/* Error in pplib. Provide default values. */
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get_default_clock_levels(clk_type, dc_clks);
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return true;
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}
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}
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pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
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if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
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if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
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pp_handle, &validation_clks)) {
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/* Error in pplib. Provide default values. */
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DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
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validation_clks.engine_max_clock = 72000;
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validation_clks.memory_max_clock = 80000;
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validation_clks.level = 0;
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}
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}
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DRM_INFO("DM_PPLIB: Validation clocks:\n");
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DRM_INFO("DM_PPLIB: engine_max_clock: %d\n",
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validation_clks.engine_max_clock);
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DRM_INFO("DM_PPLIB: memory_max_clock: %d\n",
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validation_clks.memory_max_clock);
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DRM_INFO("DM_PPLIB: level : %d\n",
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validation_clks.level);
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/* Translate 10 kHz to kHz. */
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validation_clks.engine_max_clock *= 10;
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validation_clks.memory_max_clock *= 10;
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/* Determine the highest non-boosted level from the Validation Clocks */
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if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
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for (i = 0; i < dc_clks->num_levels; i++) {
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if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
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/* This clock is higher the validation clock.
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* Than means the previous one is the highest
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* non-boosted one. */
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DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
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dc_clks->num_levels, i);
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dc_clks->num_levels = i > 0 ? i : 1;
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break;
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}
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}
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} else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
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for (i = 0; i < dc_clks->num_levels; i++) {
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if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
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DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
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dc_clks->num_levels, i);
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dc_clks->num_levels = i > 0 ? i : 1;
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break;
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}
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}
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}
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return true;
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}
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bool dm_pp_get_clock_levels_by_type_with_latency(
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const struct dc_context *ctx,
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enum dm_pp_clock_type clk_type,
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struct dm_pp_clock_levels_with_latency *clk_level_info)
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{
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struct amdgpu_device *adev = ctx->driver_context;
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void *pp_handle = adev->powerplay.pp_handle;
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struct pp_clock_levels_with_latency pp_clks = { 0 };
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const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
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if (!pp_funcs || !pp_funcs->get_clock_by_type_with_latency)
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return false;
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if (pp_funcs->get_clock_by_type_with_latency(pp_handle,
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dc_to_pp_clock_type(clk_type),
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&pp_clks))
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return false;
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pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);
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return true;
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}
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bool dm_pp_get_clock_levels_by_type_with_voltage(
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const struct dc_context *ctx,
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enum dm_pp_clock_type clk_type,
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struct dm_pp_clock_levels_with_voltage *clk_level_info)
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{
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struct amdgpu_device *adev = ctx->driver_context;
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void *pp_handle = adev->powerplay.pp_handle;
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struct pp_clock_levels_with_voltage pp_clk_info = {0};
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const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
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if (pp_funcs->get_clock_by_type_with_voltage(pp_handle,
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dc_to_pp_clock_type(clk_type),
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&pp_clk_info))
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return false;
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pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type);
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return true;
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}
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bool dm_pp_notify_wm_clock_changes(
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const struct dc_context *ctx,
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struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
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{
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/* TODO: to be implemented */
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return false;
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}
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bool dm_pp_apply_power_level_change_request(
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const struct dc_context *ctx,
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struct dm_pp_power_level_change_request *level_change_req)
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{
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/* TODO: to be implemented */
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return false;
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}
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bool dm_pp_apply_clock_for_voltage_request(
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const struct dc_context *ctx,
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struct dm_pp_clock_for_voltage_req *clock_for_voltage_req)
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{
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struct amdgpu_device *adev = ctx->driver_context;
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struct pp_display_clock_request pp_clock_request = {0};
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int ret = 0;
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pp_clock_request.clock_type = dc_to_pp_clock_type(clock_for_voltage_req->clk_type);
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pp_clock_request.clock_freq_in_khz = clock_for_voltage_req->clocks_in_khz;
|
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if (!pp_clock_request.clock_type)
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return false;
|
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if (adev->powerplay.pp_funcs->display_clock_voltage_request)
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ret = adev->powerplay.pp_funcs->display_clock_voltage_request(
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adev->powerplay.pp_handle,
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&pp_clock_request);
|
if (ret)
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return false;
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return true;
|
}
|
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bool dm_pp_get_static_clocks(
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const struct dc_context *ctx,
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struct dm_pp_static_clock_info *static_clk_info)
|
{
|
struct amdgpu_device *adev = ctx->driver_context;
|
struct amd_pp_clock_info pp_clk_info = {0};
|
int ret = 0;
|
|
if (adev->powerplay.pp_funcs->get_current_clocks)
|
ret = adev->powerplay.pp_funcs->get_current_clocks(
|
adev->powerplay.pp_handle,
|
&pp_clk_info);
|
if (ret)
|
return false;
|
|
static_clk_info->max_clocks_state = pp_to_dc_powerlevel_state(pp_clk_info.max_clocks_state);
|
static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10;
|
static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10;
|
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return true;
|
}
|
|
void pp_rv_set_display_requirement(struct pp_smu *pp,
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struct pp_smu_display_requirement_rv *req)
|
{
|
struct dc_context *ctx = pp->ctx;
|
struct amdgpu_device *adev = ctx->driver_context;
|
void *pp_handle = adev->powerplay.pp_handle;
|
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
|
struct pp_display_clock_request clock = {0};
|
|
if (!pp_funcs || !pp_funcs->display_clock_voltage_request)
|
return;
|
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clock.clock_type = amd_pp_dcf_clock;
|
clock.clock_freq_in_khz = req->hard_min_dcefclk_khz;
|
pp_funcs->display_clock_voltage_request(pp_handle, &clock);
|
|
clock.clock_type = amd_pp_f_clock;
|
clock.clock_freq_in_khz = req->hard_min_fclk_khz;
|
pp_funcs->display_clock_voltage_request(pp_handle, &clock);
|
}
|
|
void pp_rv_set_wm_ranges(struct pp_smu *pp,
|
struct pp_smu_wm_range_sets *ranges)
|
{
|
struct dc_context *ctx = pp->ctx;
|
struct amdgpu_device *adev = ctx->driver_context;
|
void *pp_handle = adev->powerplay.pp_handle;
|
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
|
struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
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struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks = wm_with_clock_ranges.wm_dmif_clocks_ranges;
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struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks = wm_with_clock_ranges.wm_mcif_clocks_ranges;
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int32_t i;
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wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
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wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
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for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
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if (ranges->reader_wm_sets[i].wm_inst > 3)
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wm_dce_clocks[i].wm_set_id = WM_SET_A;
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else
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wm_dce_clocks[i].wm_set_id =
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ranges->reader_wm_sets[i].wm_inst;
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wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
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ranges->reader_wm_sets[i].max_drain_clk_khz;
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wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
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ranges->reader_wm_sets[i].min_drain_clk_khz;
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wm_dce_clocks[i].wm_max_mem_clk_in_khz =
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ranges->reader_wm_sets[i].max_fill_clk_khz;
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wm_dce_clocks[i].wm_min_mem_clk_in_khz =
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ranges->reader_wm_sets[i].min_fill_clk_khz;
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}
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for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
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if (ranges->writer_wm_sets[i].wm_inst > 3)
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wm_soc_clocks[i].wm_set_id = WM_SET_A;
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else
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wm_soc_clocks[i].wm_set_id =
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ranges->writer_wm_sets[i].wm_inst;
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wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
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ranges->writer_wm_sets[i].max_fill_clk_khz;
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wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
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ranges->writer_wm_sets[i].min_fill_clk_khz;
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wm_soc_clocks[i].wm_max_mem_clk_in_khz =
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ranges->writer_wm_sets[i].max_drain_clk_khz;
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wm_soc_clocks[i].wm_min_mem_clk_in_khz =
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ranges->writer_wm_sets[i].min_drain_clk_khz;
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}
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pp_funcs->set_watermarks_for_clocks_ranges(pp_handle, &wm_with_clock_ranges);
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}
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void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
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{
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struct dc_context *ctx = pp->ctx;
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struct amdgpu_device *adev = ctx->driver_context;
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void *pp_handle = adev->powerplay.pp_handle;
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const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
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if (!pp_funcs || !pp_funcs->notify_smu_enable_pwe)
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return;
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pp_funcs->notify_smu_enable_pwe(pp_handle);
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}
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void dm_pp_get_funcs_rv(
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struct dc_context *ctx,
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struct pp_smu_funcs_rv *funcs)
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{
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funcs->pp_smu.ctx = ctx;
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funcs->set_display_requirement = pp_rv_set_display_requirement;
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funcs->set_wm_ranges = pp_rv_set_wm_ranges;
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funcs->set_pme_wa_enable = pp_rv_set_pme_wa_enable;
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}
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