/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <drm/drmP.h>
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#include "dm_services_types.h"
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#include "dc.h"
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#include "amdgpu.h"
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#include "amdgpu_dm.h"
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#include "amdgpu_dm_irq.h"
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/******************************************************************************
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* Private declarations.
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*****************************************************************************/
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struct handler_common_data {
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struct list_head list;
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interrupt_handler handler;
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void *handler_arg;
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/* DM which this handler belongs to */
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struct amdgpu_display_manager *dm;
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};
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struct amdgpu_dm_irq_handler_data {
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struct handler_common_data hcd;
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/* DAL irq source which registered for this interrupt. */
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enum dc_irq_source irq_source;
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};
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#define DM_IRQ_TABLE_LOCK(adev, flags) \
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spin_lock_irqsave(&adev->dm.irq_handler_list_table_lock, flags)
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#define DM_IRQ_TABLE_UNLOCK(adev, flags) \
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spin_unlock_irqrestore(&adev->dm.irq_handler_list_table_lock, flags)
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/******************************************************************************
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* Private functions.
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*****************************************************************************/
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static void init_handler_common_data(struct handler_common_data *hcd,
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void (*ih)(void *),
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void *args,
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struct amdgpu_display_manager *dm)
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{
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hcd->handler = ih;
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hcd->handler_arg = args;
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hcd->dm = dm;
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}
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/**
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* dm_irq_work_func - Handle an IRQ outside of the interrupt handler proper.
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*
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* @work: work struct
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*/
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static void dm_irq_work_func(struct work_struct *work)
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{
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struct list_head *entry;
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struct irq_list_head *irq_list_head =
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container_of(work, struct irq_list_head, work);
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struct list_head *handler_list = &irq_list_head->head;
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struct amdgpu_dm_irq_handler_data *handler_data;
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list_for_each(entry, handler_list) {
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handler_data =
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list_entry(
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entry,
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struct amdgpu_dm_irq_handler_data,
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hcd.list);
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DRM_DEBUG_KMS("DM_IRQ: work_func: for dal_src=%d\n",
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handler_data->irq_source);
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DRM_DEBUG_KMS("DM_IRQ: schedule_work: for dal_src=%d\n",
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handler_data->irq_source);
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handler_data->hcd.handler(handler_data->hcd.handler_arg);
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}
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/* Call a DAL subcomponent which registered for interrupt notification
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* at INTERRUPT_LOW_IRQ_CONTEXT.
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* (The most common use is HPD interrupt) */
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}
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/**
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* Remove a handler and return a pointer to hander list from which the
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* handler was removed.
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*/
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static struct list_head *remove_irq_handler(struct amdgpu_device *adev,
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void *ih,
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const struct dc_interrupt_params *int_params)
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{
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struct list_head *hnd_list;
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struct list_head *entry, *tmp;
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struct amdgpu_dm_irq_handler_data *handler;
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unsigned long irq_table_flags;
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bool handler_removed = false;
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enum dc_irq_source irq_source;
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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irq_source = int_params->irq_source;
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switch (int_params->int_context) {
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case INTERRUPT_HIGH_IRQ_CONTEXT:
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hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
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break;
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case INTERRUPT_LOW_IRQ_CONTEXT:
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default:
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hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
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break;
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}
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list_for_each_safe(entry, tmp, hnd_list) {
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handler = list_entry(entry, struct amdgpu_dm_irq_handler_data,
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hcd.list);
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if (ih == handler) {
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/* Found our handler. Remove it from the list. */
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list_del(&handler->hcd.list);
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handler_removed = true;
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break;
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}
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}
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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if (handler_removed == false) {
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/* Not necessarily an error - caller may not
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* know the context. */
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return NULL;
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}
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kfree(handler);
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DRM_DEBUG_KMS(
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"DM_IRQ: removed irq handler: %p for: dal_src=%d, irq context=%d\n",
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ih, int_params->irq_source, int_params->int_context);
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return hnd_list;
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}
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static bool
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validate_irq_registration_params(struct dc_interrupt_params *int_params,
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void (*ih)(void *))
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{
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if (NULL == int_params || NULL == ih) {
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DRM_ERROR("DM_IRQ: invalid input!\n");
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return false;
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}
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if (int_params->int_context >= INTERRUPT_CONTEXT_NUMBER) {
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DRM_ERROR("DM_IRQ: invalid context: %d!\n",
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int_params->int_context);
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return false;
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}
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if (!DAL_VALID_IRQ_SRC_NUM(int_params->irq_source)) {
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DRM_ERROR("DM_IRQ: invalid irq_source: %d!\n",
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int_params->irq_source);
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return false;
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}
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return true;
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}
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static bool validate_irq_unregistration_params(enum dc_irq_source irq_source,
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irq_handler_idx handler_idx)
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{
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if (DAL_INVALID_IRQ_HANDLER_IDX == handler_idx) {
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DRM_ERROR("DM_IRQ: invalid handler_idx==NULL!\n");
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return false;
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}
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if (!DAL_VALID_IRQ_SRC_NUM(irq_source)) {
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DRM_ERROR("DM_IRQ: invalid irq_source:%d!\n", irq_source);
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return false;
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}
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return true;
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}
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/******************************************************************************
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* Public functions.
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*
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* Note: caller is responsible for input validation.
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*****************************************************************************/
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void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
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struct dc_interrupt_params *int_params,
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void (*ih)(void *),
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void *handler_args)
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{
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struct list_head *hnd_list;
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struct amdgpu_dm_irq_handler_data *handler_data;
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unsigned long irq_table_flags;
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enum dc_irq_source irq_source;
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if (false == validate_irq_registration_params(int_params, ih))
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return DAL_INVALID_IRQ_HANDLER_IDX;
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handler_data = kzalloc(sizeof(*handler_data), GFP_KERNEL);
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if (!handler_data) {
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DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n");
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return DAL_INVALID_IRQ_HANDLER_IDX;
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}
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memset(handler_data, 0, sizeof(*handler_data));
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init_handler_common_data(&handler_data->hcd, ih, handler_args,
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&adev->dm);
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irq_source = int_params->irq_source;
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handler_data->irq_source = irq_source;
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/* Lock the list, add the handler. */
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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switch (int_params->int_context) {
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case INTERRUPT_HIGH_IRQ_CONTEXT:
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hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
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break;
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case INTERRUPT_LOW_IRQ_CONTEXT:
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default:
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hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
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break;
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}
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list_add_tail(&handler_data->hcd.list, hnd_list);
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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/* This pointer will be stored by code which requested interrupt
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* registration.
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* The same pointer will be needed in order to unregister the
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* interrupt. */
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DRM_DEBUG_KMS(
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"DM_IRQ: added irq handler: %p for: dal_src=%d, irq context=%d\n",
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handler_data,
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irq_source,
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int_params->int_context);
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return handler_data;
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}
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void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
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enum dc_irq_source irq_source,
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void *ih)
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{
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struct list_head *handler_list;
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struct dc_interrupt_params int_params;
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int i;
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if (false == validate_irq_unregistration_params(irq_source, ih))
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return;
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memset(&int_params, 0, sizeof(int_params));
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int_params.irq_source = irq_source;
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for (i = 0; i < INTERRUPT_CONTEXT_NUMBER; i++) {
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int_params.int_context = i;
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handler_list = remove_irq_handler(adev, ih, &int_params);
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if (handler_list != NULL)
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break;
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}
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if (handler_list == NULL) {
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/* If we got here, it means we searched all irq contexts
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* for this irq source, but the handler was not found. */
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DRM_ERROR(
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"DM_IRQ: failed to find irq handler:%p for irq_source:%d!\n",
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ih, irq_source);
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}
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}
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int amdgpu_dm_irq_init(struct amdgpu_device *adev)
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{
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int src;
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struct irq_list_head *lh;
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DRM_DEBUG_KMS("DM_IRQ\n");
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spin_lock_init(&adev->dm.irq_handler_list_table_lock);
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for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
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/* low context handler list init */
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lh = &adev->dm.irq_handler_list_low_tab[src];
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INIT_LIST_HEAD(&lh->head);
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INIT_WORK(&lh->work, dm_irq_work_func);
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/* high context handler init */
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INIT_LIST_HEAD(&adev->dm.irq_handler_list_high_tab[src]);
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}
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return 0;
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}
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/* DM IRQ and timer resource release */
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void amdgpu_dm_irq_fini(struct amdgpu_device *adev)
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{
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int src;
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struct irq_list_head *lh;
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unsigned long irq_table_flags;
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DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n");
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for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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/* The handler was removed from the table,
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* it means it is safe to flush all the 'work'
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* (because no code can schedule a new one). */
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lh = &adev->dm.irq_handler_list_low_tab[src];
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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flush_work(&lh->work);
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}
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}
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int amdgpu_dm_irq_suspend(struct amdgpu_device *adev)
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{
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int src;
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struct list_head *hnd_list_h;
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struct list_head *hnd_list_l;
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unsigned long irq_table_flags;
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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DRM_DEBUG_KMS("DM_IRQ: suspend\n");
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/**
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* Disable HW interrupt for HPD and HPDRX only since FLIP and VBLANK
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* will be disabled from manage_dm_interrupts on disable CRTC.
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*/
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for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
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hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
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hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
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if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
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dc_interrupt_set(adev->dm.dc, src, false);
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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flush_work(&adev->dm.irq_handler_list_low_tab[src].work);
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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}
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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return 0;
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}
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int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)
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{
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int src;
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struct list_head *hnd_list_h, *hnd_list_l;
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unsigned long irq_table_flags;
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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DRM_DEBUG_KMS("DM_IRQ: early resume\n");
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/* re-enable short pulse interrupts HW interrupt */
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for (src = DC_IRQ_SOURCE_HPD1RX; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
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hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
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hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
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if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
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dc_interrupt_set(adev->dm.dc, src, true);
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}
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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return 0;
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}
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int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)
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{
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int src;
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struct list_head *hnd_list_h, *hnd_list_l;
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unsigned long irq_table_flags;
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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DRM_DEBUG_KMS("DM_IRQ: resume\n");
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/**
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* Renable HW interrupt for HPD and only since FLIP and VBLANK
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* will be enabled from manage_dm_interrupts on enable CRTC.
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*/
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for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6; src++) {
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hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
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hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
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if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
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dc_interrupt_set(adev->dm.dc, src, true);
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}
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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return 0;
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}
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/**
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* amdgpu_dm_irq_schedule_work - schedule all work items registered for the
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* "irq_source".
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*/
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static void amdgpu_dm_irq_schedule_work(struct amdgpu_device *adev,
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enum dc_irq_source irq_source)
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{
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unsigned long irq_table_flags;
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struct work_struct *work = NULL;
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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if (!list_empty(&adev->dm.irq_handler_list_low_tab[irq_source].head))
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work = &adev->dm.irq_handler_list_low_tab[irq_source].work;
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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if (work) {
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if (!schedule_work(work))
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DRM_INFO("amdgpu_dm_irq_schedule_work FAILED src %d\n",
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irq_source);
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}
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}
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/** amdgpu_dm_irq_immediate_work
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* Callback high irq work immediately, don't send to work queue
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*/
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static void amdgpu_dm_irq_immediate_work(struct amdgpu_device *adev,
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enum dc_irq_source irq_source)
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{
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struct amdgpu_dm_irq_handler_data *handler_data;
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struct list_head *entry;
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unsigned long irq_table_flags;
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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list_for_each(
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entry,
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&adev->dm.irq_handler_list_high_tab[irq_source]) {
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handler_data =
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list_entry(
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entry,
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struct amdgpu_dm_irq_handler_data,
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hcd.list);
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/* Call a subcomponent which registered for immediate
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* interrupt notification */
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handler_data->hcd.handler(handler_data->hcd.handler_arg);
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}
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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}
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/*
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* amdgpu_dm_irq_handler
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*
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* Generic IRQ handler, calls all registered high irq work immediately, and
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* schedules work for low irq
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*/
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static int amdgpu_dm_irq_handler(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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enum dc_irq_source src =
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dc_interrupt_to_irq_source(
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adev->dm.dc,
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entry->src_id,
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entry->src_data[0]);
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dc_interrupt_ack(adev->dm.dc, src);
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/* Call high irq work immediately */
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amdgpu_dm_irq_immediate_work(adev, src);
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/*Schedule low_irq work */
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amdgpu_dm_irq_schedule_work(adev, src);
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return 0;
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}
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static enum dc_irq_source amdgpu_dm_hpd_to_dal_irq_source(unsigned type)
|
{
|
switch (type) {
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case AMDGPU_HPD_1:
|
return DC_IRQ_SOURCE_HPD1;
|
case AMDGPU_HPD_2:
|
return DC_IRQ_SOURCE_HPD2;
|
case AMDGPU_HPD_3:
|
return DC_IRQ_SOURCE_HPD3;
|
case AMDGPU_HPD_4:
|
return DC_IRQ_SOURCE_HPD4;
|
case AMDGPU_HPD_5:
|
return DC_IRQ_SOURCE_HPD5;
|
case AMDGPU_HPD_6:
|
return DC_IRQ_SOURCE_HPD6;
|
default:
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return DC_IRQ_SOURCE_INVALID;
|
}
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}
|
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static int amdgpu_dm_set_hpd_irq_state(struct amdgpu_device *adev,
|
struct amdgpu_irq_src *source,
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unsigned type,
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enum amdgpu_interrupt_state state)
|
{
|
enum dc_irq_source src = amdgpu_dm_hpd_to_dal_irq_source(type);
|
bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
|
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dc_interrupt_set(adev->dm.dc, src, st);
|
return 0;
|
}
|
|
static inline int dm_irq_state(struct amdgpu_device *adev,
|
struct amdgpu_irq_src *source,
|
unsigned crtc_id,
|
enum amdgpu_interrupt_state state,
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const enum irq_type dal_irq_type,
|
const char *func)
|
{
|
bool st;
|
enum dc_irq_source irq_source;
|
|
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
|
|
if (!acrtc) {
|
DRM_ERROR(
|
"%s: crtc is NULL at id :%d\n",
|
func,
|
crtc_id);
|
return 0;
|
}
|
|
if (acrtc->otg_inst == -1)
|
return 0;
|
|
irq_source = dal_irq_type + acrtc->otg_inst;
|
|
st = (state == AMDGPU_IRQ_STATE_ENABLE);
|
|
dc_interrupt_set(adev->dm.dc, irq_source, st);
|
return 0;
|
}
|
|
static int amdgpu_dm_set_pflip_irq_state(struct amdgpu_device *adev,
|
struct amdgpu_irq_src *source,
|
unsigned crtc_id,
|
enum amdgpu_interrupt_state state)
|
{
|
return dm_irq_state(
|
adev,
|
source,
|
crtc_id,
|
state,
|
IRQ_TYPE_PFLIP,
|
__func__);
|
}
|
|
static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev,
|
struct amdgpu_irq_src *source,
|
unsigned crtc_id,
|
enum amdgpu_interrupt_state state)
|
{
|
return dm_irq_state(
|
adev,
|
source,
|
crtc_id,
|
state,
|
IRQ_TYPE_VBLANK,
|
__func__);
|
}
|
|
static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = {
|
.set = amdgpu_dm_set_crtc_irq_state,
|
.process = amdgpu_dm_irq_handler,
|
};
|
|
static const struct amdgpu_irq_src_funcs dm_pageflip_irq_funcs = {
|
.set = amdgpu_dm_set_pflip_irq_state,
|
.process = amdgpu_dm_irq_handler,
|
};
|
|
static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = {
|
.set = amdgpu_dm_set_hpd_irq_state,
|
.process = amdgpu_dm_irq_handler,
|
};
|
|
void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
|
{
|
|
adev->crtc_irq.num_types = adev->mode_info.num_crtc;
|
adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
|
|
adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
|
adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs;
|
|
adev->hpd_irq.num_types = adev->mode_info.num_hpd;
|
adev->hpd_irq.funcs = &dm_hpd_irq_funcs;
|
}
|
|
/*
|
* amdgpu_dm_hpd_init - hpd setup callback.
|
*
|
* @adev: amdgpu_device pointer
|
*
|
* Setup the hpd pins used by the card (evergreen+).
|
* Enable the pin, set the polarity, and enable the hpd interrupts.
|
*/
|
void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
|
{
|
struct drm_device *dev = adev->ddev;
|
struct drm_connector *connector;
|
|
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
|
struct amdgpu_dm_connector *amdgpu_dm_connector =
|
to_amdgpu_dm_connector(connector);
|
|
const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
|
|
if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
|
dc_interrupt_set(adev->dm.dc,
|
dc_link->irq_source_hpd,
|
true);
|
}
|
|
if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
|
dc_interrupt_set(adev->dm.dc,
|
dc_link->irq_source_hpd_rx,
|
true);
|
}
|
}
|
}
|
|
/**
|
* amdgpu_dm_hpd_fini - hpd tear down callback.
|
*
|
* @adev: amdgpu_device pointer
|
*
|
* Tear down the hpd pins used by the card (evergreen+).
|
* Disable the hpd interrupts.
|
*/
|
void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
|
{
|
struct drm_device *dev = adev->ddev;
|
struct drm_connector *connector;
|
|
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
|
struct amdgpu_dm_connector *amdgpu_dm_connector =
|
to_amdgpu_dm_connector(connector);
|
const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
|
|
dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, false);
|
|
if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
|
dc_interrupt_set(adev->dm.dc,
|
dc_link->irq_source_hpd_rx,
|
false);
|
}
|
}
|
}
|
