/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS1021AQDS_QIXIS_H__
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#define __LS1021AQDS_QIXIS_H__
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/* Definitions of QIXIS Registers for LS1021AQDS */
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/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
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#define BRDCFG4_EMISEL_MASK 0xe0
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#define BRDCFG4_EMISEL_SHIFT 5
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/* SYSCLK */
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#define QIXIS_SYSCLK_66 0x0
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#define QIXIS_SYSCLK_83 0x1
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#define QIXIS_SYSCLK_100 0x2
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#define QIXIS_SYSCLK_125 0x3
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#define QIXIS_SYSCLK_133 0x4
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#define QIXIS_SYSCLK_150 0x5
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#define QIXIS_SYSCLK_160 0x6
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#define QIXIS_SYSCLK_166 0x7
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#define QIXIS_SYSCLK_64 0x8
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/* DDRCLK */
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#define QIXIS_DDRCLK_66 0x0
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#define QIXIS_DDRCLK_100 0x1
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#define QIXIS_DDRCLK_125 0x2
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#define QIXIS_DDRCLK_133 0x3
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#define QIXIS_SRDS1CLK_100 0x0
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#define QIXIS_DCU_BRDCFG5 0x55
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#endif
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