* ARM Performance Monitor Units
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ARM cores often have a PMU for counting cpu and cache events like cache misses
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and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
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representation in the device tree should be done as under:-
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Required properties:
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- compatible : should be one of
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"apm,potenza-pmu"
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"arm,armv8-pmuv3"
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"arm,cortex-a73-pmu"
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"arm,cortex-a72-pmu"
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"arm,cortex-a57-pmu"
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"arm,cortex-a53-pmu"
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"arm,cortex-a35-pmu"
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"arm,cortex-a17-pmu"
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"arm,cortex-a15-pmu"
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"arm,cortex-a12-pmu"
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"arm,cortex-a9-pmu"
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"arm,cortex-a8-pmu"
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"arm,cortex-a7-pmu"
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"arm,cortex-a5-pmu"
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"arm,arm11mpcore-pmu"
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"arm,arm1176-pmu"
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"arm,arm1136-pmu"
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"brcm,vulcan-pmu"
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"cavium,thunder-pmu"
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"qcom,scorpion-pmu"
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"qcom,scorpion-mp-pmu"
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"qcom,krait-pmu"
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- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
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interrupt (PPI) then 1 interrupt should be specified.
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Optional properties:
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- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
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nodes corresponding directly to the affinity of
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the SPIs listed in the interrupts property.
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When using a PPI, specifies a list of phandles to CPU
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nodes corresponding to the set of CPUs which have
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a PMU of this type signalling the PPI listed in the
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interrupts property, unless this is already specified
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by the PPI interrupt specifier itself (in which case
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the interrupt-affinity property shouldn't be present).
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This property should be present when there is more than
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a single SPI.
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- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
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events.
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- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register
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(SDER) is accessible. This will cause the driver to do
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any setup required that is only possible in ARMv7 secure
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state. If not present the ARMv7 SDER will not be touched,
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which means the PMU may fail to operate unless external
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code (bootloader or security monitor) has performed the
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appropriate initialisation. Note that this property is
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not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
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in Non-secure state.
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Example:
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <100 101>;
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};
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