// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Rockchip Electronics Co., Ltd
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*
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* Based on phy-rockchip-inno-usb3.c in Linux Kernel.
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <dm/of_access.h>
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#include <generic-phy.h>
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#include <power/regulator.h>
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#include <regmap.h>
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#include <reset.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#define usleep_range(a, b) udelay((b))
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#define U3PHY_PORT_NUM 2
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#define U3PHY_MAX_CLKS 4
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#define BIT_WRITEABLE_SHIFT 16
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#define SCHEDULE_DELAY (60 * HZ)
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#define U3PHY_APB_RST BIT(0)
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#define U3PHY_POR_RST BIT(1)
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#define U3PHY_MAC_RST BIT(2)
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struct rockchip_u3phy;
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struct rockchip_u3phy_port;
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enum rockchip_u3phy_type {
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U3PHY_TYPE_PIPE,
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U3PHY_TYPE_UTMI,
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};
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enum rockchip_u3phy_pipe_pwr {
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PIPE_PWR_P0 = 0,
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PIPE_PWR_P1 = 1,
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PIPE_PWR_P2 = 2,
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PIPE_PWR_P3 = 3,
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PIPE_PWR_MAX = 4,
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};
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enum rockchip_u3phy_rest_req {
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U3_POR_RSTN = 0,
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U2_POR_RSTN = 1,
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PIPE_MAC_RSTN = 2,
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UTMI_MAC_RSTN = 3,
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PIPE_APB_RSTN = 4,
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UTMI_APB_RSTN = 5,
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U3PHY_RESET_MAX = 6,
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};
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enum rockchip_u3phy_utmi_state {
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PHY_UTMI_HS_ONLINE = 0,
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PHY_UTMI_DISCONNECT = 1,
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PHY_UTMI_CONNECT = 2,
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PHY_UTMI_FS_LS_ONLINE = 4,
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};
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/*
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* @rvalue: reset value
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* @dvalue: desired value
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*/
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struct u3phy_reg {
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unsigned int offset;
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unsigned int bitend;
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unsigned int bitstart;
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unsigned int rvalue;
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unsigned int dvalue;
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};
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struct rockchip_u3phy_grfcfg {
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struct u3phy_reg um_suspend;
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struct u3phy_reg ls_det_en;
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struct u3phy_reg ls_det_st;
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struct u3phy_reg um_ls;
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struct u3phy_reg um_hstdct;
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struct u3phy_reg u2_only_ctrl;
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struct u3phy_reg u3_disable;
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struct u3phy_reg pp_pwr_st;
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struct u3phy_reg pp_pwr_en[PIPE_PWR_MAX];
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};
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/**
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* struct rockchip_u3phy_apbcfg: usb3-phy apb configuration.
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* @u2_pre_emp: usb2-phy pre-emphasis tuning.
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* @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning.
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* @u2_odt_tuning: usb2-phy odt 45ohm tuning.
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*/
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struct rockchip_u3phy_apbcfg {
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unsigned int u2_pre_emp;
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unsigned int u2_pre_emp_sth;
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unsigned int u2_odt_tuning;
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};
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struct rockchip_u3phy_cfg {
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unsigned int reg;
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const struct rockchip_u3phy_grfcfg grfcfg;
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int (*phy_tuning)(struct rockchip_u3phy *u3phy,
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struct rockchip_u3phy_port *u3phy_port,
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const struct device_node *child_np);
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};
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struct rockchip_u3phy_port {
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void __iomem *base;
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unsigned int index;
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unsigned char type;
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bool refclk_25m_quirk;
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struct mutex mutex; /* mutex for updating register */
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};
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struct rockchip_u3phy {
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struct udevice *dev;
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struct regmap *u3phy_grf;
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struct regmap *grf;
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struct udevice *vbus_supply;
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struct reset_ctl rsts[U3PHY_RESET_MAX];
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struct rockchip_u3phy_apbcfg apbcfg;
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const struct rockchip_u3phy_cfg *cfgs;
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struct rockchip_u3phy_port ports[U3PHY_PORT_NUM];
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};
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static inline int param_write(void __iomem *base,
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const struct u3phy_reg *reg, bool desired)
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{
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unsigned int val, mask;
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unsigned int tmp = desired ? reg->dvalue : reg->rvalue;
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int ret = 0;
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mask = GENMASK(reg->bitend, reg->bitstart);
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val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
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ret = regmap_write(base, reg->offset, val);
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return ret;
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}
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static inline bool param_exped(void __iomem *base,
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const struct u3phy_reg *reg,
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unsigned int value)
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{
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int ret;
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unsigned int tmp, orig;
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unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
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ret = regmap_read(base, reg->offset, &orig);
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if (ret)
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return false;
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tmp = (orig & mask) >> reg->bitstart;
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return tmp == value;
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}
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int rockchip_u3phy_uboot_init(void)
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{
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struct udevice *udev;
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int ret;
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ret = uclass_get_device_by_name(UCLASS_PHY, "usb3-phy", &udev);
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if (ret)
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pr_err("%s: get usb3-phy node failed: %d\n", __func__, ret);
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(void)udev;
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return ret;
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}
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static int rockchip_u3phy_init(struct phy *phy)
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{
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return 0;
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}
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static int rockchip_u3phy_exit(struct phy *phy)
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{
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return 0;
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}
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static int rockchip_u3phy_power_on(struct phy *phy)
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{
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struct udevice *parent = dev_get_parent(phy->dev);
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struct rockchip_u3phy *u3phy = dev_get_priv(parent);
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int ret = 0;
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/* Vbus regulator */
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if (!u3phy->vbus_supply) {
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ret = device_get_supply_regulator(parent, "vbus-supply",
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&u3phy->vbus_supply);
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if (ret == -ENOENT) {
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pr_info("%s: Can't get VBus regulator!\n", __func__);
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return 0;
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}
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ret = regulator_set_enable(u3phy->vbus_supply, true);
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if (ret) {
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pr_err("%s: Failed to set VBus supply\n", __func__);
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return ret;
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}
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}
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return 0;
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}
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static int rockchip_u3phy_power_off(struct phy *phy)
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{
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struct udevice *parent = dev_get_parent(phy->dev);
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struct rockchip_u3phy *u3phy = dev_get_priv(parent);
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int ret = 0;
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/* Turn off vbus regulator */
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if (u3phy->vbus_supply) {
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ret = regulator_set_enable(u3phy->vbus_supply, false);
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if (ret) {
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pr_err("%s: Failed to set VBus supply\n", __func__);
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return ret;
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}
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u3phy->vbus_supply = NULL;
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}
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return 0;
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}
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static int rockchip_u3phy_bind(struct udevice *parent)
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{
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struct udevice *dev;
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ofnode node;
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const char *name;
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int ret;
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dev_for_each_subnode(node, parent) {
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if (!ofnode_valid(node)) {
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debug("%s: %s subnode not found", __func__, parent->name);
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return -ENXIO;
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}
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name = ofnode_get_name(node);
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debug("%s: subnode %s\n", __func__, name);
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ret = device_bind_driver_to_node(parent, "rockchip_u3phy_port",
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name, node, &dev);
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if (ret) {
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pr_err("%s: '%s' cannot bind 'rockchip_u3phy_port'\n",
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__func__, name);
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return ret;
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}
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}
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return 0;
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}
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static const char *get_rest_name(enum rockchip_u3phy_rest_req rst)
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{
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switch (rst) {
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case U2_POR_RSTN:
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return "u3phy-u2-por";
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case U3_POR_RSTN:
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return "u3phy-u3-por";
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case PIPE_MAC_RSTN:
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return "u3phy-pipe-mac";
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case UTMI_MAC_RSTN:
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return "u3phy-utmi-mac";
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case UTMI_APB_RSTN:
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return "u3phy-utmi-apb";
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case PIPE_APB_RSTN:
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return "u3phy-pipe-apb";
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default:
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return "invalid";
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}
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}
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static void rockchip_u3phy_rest_deassert(struct rockchip_u3phy *u3phy,
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unsigned int flag)
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{
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int rst;
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if (flag & U3PHY_APB_RST) {
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dev_dbg(u3phy->dev, "deassert APB bus interface reset\n");
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for (rst = PIPE_APB_RSTN; rst <= UTMI_APB_RSTN; rst++) {
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if (u3phy->rsts[rst].dev)
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reset_deassert(&u3phy->rsts[rst]);
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}
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}
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if (flag & U3PHY_POR_RST) {
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usleep_range(12, 15);
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dev_dbg(u3phy->dev, "deassert u2 and u3 phy power on reset\n");
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for (rst = U3_POR_RSTN; rst <= U2_POR_RSTN; rst++) {
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if (u3phy->rsts[rst].dev)
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reset_deassert(&u3phy->rsts[rst]);
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}
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}
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if (flag & U3PHY_MAC_RST) {
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usleep_range(1200, 1500);
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dev_dbg(u3phy->dev, "deassert pipe and utmi MAC reset\n");
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for (rst = PIPE_MAC_RSTN; rst <= UTMI_MAC_RSTN; rst++)
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if (u3phy->rsts[rst].dev)
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reset_deassert(&u3phy->rsts[rst]);
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}
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}
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static void rockchip_u3phy_rest_assert(struct rockchip_u3phy *u3phy)
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{
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int rst;
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dev_dbg(u3phy->dev, "assert u3phy reset\n");
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for (rst = 0; rst < U3PHY_RESET_MAX; rst++)
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if (u3phy->rsts[rst].dev)
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reset_assert(&u3phy->rsts[rst]);
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}
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static int rockchip_u3phy_parse_dt(struct rockchip_u3phy *u3phy,
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struct udevice *udev)
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{
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int i, ret = 0;
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for (i = 0; i < U3PHY_RESET_MAX; i++) {
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ret = reset_get_by_name(udev, get_rest_name(i),
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&u3phy->rsts[i]);
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if (ret) {
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dev_info(udev, "no %s reset control specified\n",
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get_rest_name(i));
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}
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}
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return ret;
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}
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static int rockchip_u3phy_port_init(struct rockchip_u3phy *u3phy,
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struct rockchip_u3phy_port *u3phy_port,
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const struct device_node *child_np)
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{
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int ret;
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dev_dbg(u3phy->dev, "u3phy port initialize\n");
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mutex_init(&u3phy_port->mutex);
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u3phy_port->base = (void __iomem *)ofnode_get_addr(np_to_ofnode(child_np));
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if (IS_ERR(u3phy_port->base)) {
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dev_err(u3phy->dev, "failed to remap phy regs\n");
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return PTR_ERR(u3phy_port->base);
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}
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if (!of_node_cmp(child_np->name, "pipe")) {
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u3phy_port->type = U3PHY_TYPE_PIPE;
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u3phy_port->refclk_25m_quirk =
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ofnode_read_bool(np_to_ofnode(child_np),
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"rockchip,refclk-25m-quirk");
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} else {
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u3phy_port->type = U3PHY_TYPE_UTMI;
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}
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if (u3phy->cfgs->phy_tuning) {
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dev_dbg(u3phy->dev, "do u3phy tuning\n");
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ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int rockchip_u3phy_probe(struct udevice *udev)
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{
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const struct udevice_id *of_match = udev->driver->of_match;
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struct rockchip_u3phy *u3phy = dev_get_priv(udev);
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const struct rockchip_u3phy_cfg *phy_cfgs;
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ofnode child_np;
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u32 reg[2], index;
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int ret = 0;
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while (of_match->compatible) {
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if (device_is_compatible(udev, of_match->compatible))
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break;
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of_match++;
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}
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if (!of_match || !of_match->data) {
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dev_err(udev, "phy-cfgs are not assigned!\n");
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return -EINVAL;
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}
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if (ofnode_read_u32_array(dev_ofnode(udev), "reg", reg, 2)) {
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dev_err(udev, "could not read reg\n");
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return -EINVAL;
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}
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u3phy->dev = udev;
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phy_cfgs = (const struct rockchip_u3phy_cfg *)of_match->data;
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/* find out a proper config which can be matched with dt. */
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index = 0;
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while (phy_cfgs[index].reg) {
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if (phy_cfgs[index].reg == reg[1]) {
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u3phy->cfgs = &phy_cfgs[index];
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break;
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}
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++index;
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}
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if (!u3phy->cfgs) {
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dev_err(udev, "no phy-cfgs can be matched\n");
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return -EINVAL;
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}
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ret = rockchip_u3phy_parse_dt(u3phy, udev);
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if (ret) {
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dev_err(udev, "parse dt failed, ret(%d)\n", ret);
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return ret;
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}
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rockchip_u3phy_rest_assert(u3phy);
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rockchip_u3phy_rest_deassert(u3phy, U3PHY_APB_RST | U3PHY_POR_RST);
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index = 0;
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ofnode_for_each_subnode(child_np, udev->node) {
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struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index];
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u3phy_port->index = index;
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ret = rockchip_u3phy_port_init(u3phy, u3phy_port,
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ofnode_to_np(child_np));
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if (ret) {
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dev_err(udev, "u3phy port init failed,ret(%d)\n", ret);
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goto put_child;
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}
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/* to prevent out of boundary */
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if (++index >= U3PHY_PORT_NUM)
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break;
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}
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rockchip_u3phy_rest_deassert(u3phy, U3PHY_MAC_RST);
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dev_info(udev, "Rockchip u3phy initialized successfully\n");
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return 0;
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put_child:
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of_node_put(ofnode_to_np(child_np));
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return ret;
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}
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static int rk3328_u3phy_tuning(struct rockchip_u3phy *u3phy,
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struct rockchip_u3phy_port *u3phy_port,
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const struct device_node *child_np)
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{
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if (u3phy_port->type == U3PHY_TYPE_UTMI) {
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/*
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* For rk3328 SoC, pre-emphasis and pre-emphasis strength must
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* be written as one fixed value as below.
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*
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* Dissimilarly, the odt 45ohm value should be flexibly tuninged
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* for the different boards to adjust HS eye height, so its
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* value can be assigned in DT in code design.
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*/
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/* {bits[2:0]=111}: always enable pre-emphasis */
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u3phy->apbcfg.u2_pre_emp = 0x0f;
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/* {bits[5:3]=000}: pre-emphasis strength as the weakest */
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u3phy->apbcfg.u2_pre_emp_sth = 0x41;
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/* {bits[4:0]=10101}: odt 45ohm tuning */
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u3phy->apbcfg.u2_odt_tuning = 0xb5;
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/* optional override of the odt 45ohm tuning */
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ofnode_read_u32(np_to_ofnode(child_np),
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"rockchip,odt-val-tuning",
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&u3phy->apbcfg.u2_odt_tuning);
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writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030);
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writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040);
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writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c);
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} else if (u3phy_port->type == U3PHY_TYPE_PIPE) {
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if (u3phy_port->refclk_25m_quirk) {
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dev_dbg(u3phy->dev, "switch to 25m refclk\n");
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/* ref clk switch to 25M */
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writel(0x64, u3phy_port->base + 0x11c);
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writel(0x64, u3phy_port->base + 0x028);
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writel(0x01, u3phy_port->base + 0x020);
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writel(0x21, u3phy_port->base + 0x030);
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writel(0x06, u3phy_port->base + 0x108);
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writel(0x00, u3phy_port->base + 0x118);
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} else {
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/* configure for 24M ref clk */
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writel(0x80, u3phy_port->base + 0x10c);
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writel(0x01, u3phy_port->base + 0x118);
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writel(0x38, u3phy_port->base + 0x11c);
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writel(0x83, u3phy_port->base + 0x020);
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writel(0x02, u3phy_port->base + 0x108);
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}
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/* Enable SSC */
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udelay(3);
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writel(0x08, u3phy_port->base + 0x000);
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writel(0x0c, u3phy_port->base + 0x120);
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/* Tuning Rx for compliance RJTL test */
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writel(0x70, u3phy_port->base + 0x150);
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writel(0x12, u3phy_port->base + 0x0c8);
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writel(0x05, u3phy_port->base + 0x148);
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writel(0x08, u3phy_port->base + 0x068);
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writel(0xf0, u3phy_port->base + 0x1c4);
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writel(0xff, u3phy_port->base + 0x070);
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writel(0x0f, u3phy_port->base + 0x06c);
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writel(0xe0, u3phy_port->base + 0x060);
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|
/*
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* Tuning Tx to increase the bias current
|
* used in TX driver and RX EQ, it can
|
* also increase the voltage of LFPS.
|
*/
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writel(0x08, u3phy_port->base + 0x180);
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} else {
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dev_err(u3phy->dev, "invalid u3phy port type\n");
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return -EINVAL;
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}
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|
return 0;
|
}
|
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static struct phy_ops rockchip_u3phy_ops = {
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.init = rockchip_u3phy_init,
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.exit = rockchip_u3phy_exit,
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.power_on= rockchip_u3phy_power_on,
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.power_off= rockchip_u3phy_power_off,
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};
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static const struct rockchip_u3phy_cfg rk3328_u3phy_cfgs[] = {
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{
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.reg = 0xff470000,
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.grfcfg = {
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.um_suspend = { 0x0004, 15, 0, 0x1452, 0x15d1 },
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.u2_only_ctrl = { 0x0020, 15, 15, 0, 1 },
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.um_ls = { 0x0030, 5, 4, 0, 1 },
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.um_hstdct = { 0x0030, 7, 7, 0, 1 },
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.ls_det_en = { 0x0040, 0, 0, 0, 1 },
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.ls_det_st = { 0x0044, 0, 0, 0, 1 },
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.pp_pwr_st = { 0x0034, 14, 13, 0, 0},
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.pp_pwr_en = { {0x0020, 14, 0, 0x0014, 0x0005},
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{0x0020, 14, 0, 0x0014, 0x000d},
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{0x0020, 14, 0, 0x0014, 0x0015},
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{0x0020, 14, 0, 0x0014, 0x001d} },
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.u3_disable = { 0x04c4, 15, 0, 0x1100, 0x101},
|
},
|
.phy_tuning = rk3328_u3phy_tuning,
|
},
|
{ /* sentinel */ }
|
};
|
|
static const struct udevice_id rockchip_u3phy_dt_match[] = {
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{ .compatible = "rockchip,rk3328-u3phy", .data = (ulong)&rk3328_u3phy_cfgs },
|
{}
|
};
|
|
U_BOOT_DRIVER(rockchip_u3phy_port) = {
|
.name = "rockchip_u3phy_port",
|
.id = UCLASS_PHY,
|
.ops = &rockchip_u3phy_ops,
|
};
|
|
U_BOOT_DRIVER(rockchip_u3phy) = {
|
.name = "rockchip_u3phy",
|
.id = UCLASS_PHY,
|
.of_match = rockchip_u3phy_dt_match,
|
.probe = rockchip_u3phy_probe,
|
.bind = rockchip_u3phy_bind,
|
.priv_auto_alloc_size = sizeof(struct rockchip_u3phy),
|
};
|
