/*
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* Copyright (C) 2015-2016 Marvell International Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _UTMI_PHY_H_
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#define _UTMI_PHY_H_
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#define UTMI_USB_CFG_DEVICE_EN_OFFSET 0
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#define UTMI_USB_CFG_DEVICE_EN_MASK \
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(0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET)
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#define UTMI_USB_CFG_DEVICE_MUX_OFFSET 1
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#define UTMI_USB_CFG_DEVICE_MUX_MASK \
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(0x1 << UTMI_USB_CFG_DEVICE_MUX_OFFSET)
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#define UTMI_USB_CFG_PLL_OFFSET 25
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#define UTMI_USB_CFG_PLL_MASK \
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(0x1 << UTMI_USB_CFG_PLL_OFFSET)
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#define UTMI_PHY_CFG_PU_OFFSET 5
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#define UTMI_PHY_CFG_PU_MASK \
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(0x1 << UTMI_PHY_CFG_PU_OFFSET)
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#define UTMI_PLL_CTRL_REG 0x0
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#define UTMI_PLL_CTRL_REFDIV_OFFSET 0
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#define UTMI_PLL_CTRL_REFDIV_MASK \
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(0x7f << UTMI_PLL_CTRL_REFDIV_OFFSET)
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#define UTMI_PLL_CTRL_FBDIV_OFFSET 16
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#define UTMI_PLL_CTRL_FBDIV_MASK \
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(0x1FF << UTMI_PLL_CTRL_FBDIV_OFFSET)
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#define UTMI_PLL_CTRL_SEL_LPFR_OFFSET 28
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#define UTMI_PLL_CTRL_SEL_LPFR_MASK \
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(0x3 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET)
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#define UTMI_PLL_CTRL_PLL_RDY_OFFSET 31
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#define UTMI_PLL_CTRL_PLL_RDY_MASK \
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(0x1 << UTMI_PLL_CTRL_PLL_RDY_OFFSET)
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#define UTMI_CALIB_CTRL_REG 0x8
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#define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8
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#define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK \
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(0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET)
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#define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23
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#define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK \
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(0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET)
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#define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31
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#define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK \
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(0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET)
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#define UTMI_TX_CH_CTRL_REG 0xC
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#define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET 12
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#define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK \
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(0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET)
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#define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16
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#define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK \
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(0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET)
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#define UTMI_RX_CH_CTRL0_REG 0x14
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#define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15
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#define UTMI_RX_CH_CTRL0_SQ_DET_MASK \
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(0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)
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#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28
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#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK \
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(0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET)
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#define UTMI_RX_CH_CTRL1_REG 0x18
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#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0
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#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK \
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(0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
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#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3
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#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK \
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(0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET)
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#define UTMI_CTRL_STATUS0_REG 0x24
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#define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET 22
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#define UTMI_CTRL_STATUS0_SUSPENDM_MASK \
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(0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET)
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#define UTMI_CTRL_STATUS0_TEST_SEL_OFFSET 25
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#define UTMI_CTRL_STATUS0_TEST_SEL_MASK \
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(0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET)
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#define UTMI_CHGDTC_CTRL_REG 0x38
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#define UTMI_CHGDTC_CTRL_VDAT_OFFSET 8
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#define UTMI_CHGDTC_CTRL_VDAT_MASK \
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(0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET)
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#define UTMI_CHGDTC_CTRL_VSRC_OFFSET 10
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#define UTMI_CHGDTC_CTRL_VSRC_MASK \
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(0x3 << UTMI_CHGDTC_CTRL_VSRC_OFFSET)
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#endif /* _UTMI_PHY_H_ */
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