/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* AMD ALSA SoC PCM Driver
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*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*/
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#include "chip_offset_byte.h"
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#include <sound/pcm.h>
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#define I2S_SP_INSTANCE 0x01
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#define I2S_BT_INSTANCE 0x02
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#define TDM_ENABLE 1
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#define TDM_DISABLE 0
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#define ACP3x_DEVS 4
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#define ACP3x_PHY_BASE_ADDRESS 0x1240000
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#define ACP3x_I2S_MODE 0
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#define ACP3x_REG_START 0x1240000
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#define ACP3x_REG_END 0x1250200
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#define ACP3x_I2STDM_REG_START 0x1242400
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#define ACP3x_I2STDM_REG_END 0x1242410
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#define ACP3x_BT_TDM_REG_START 0x1242800
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#define ACP3x_BT_TDM_REG_END 0x1242810
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#define I2S_MODE 0x04
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#define I2S_RX_THRESHOLD 27
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#define I2S_TX_THRESHOLD 28
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#define BT_TX_THRESHOLD 26
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#define BT_RX_THRESHOLD 25
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#define ACP_ERR_INTR_MASK 29
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#define ACP3x_POWER_ON 0x00
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#define ACP3x_POWER_ON_IN_PROGRESS 0x01
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#define ACP3x_POWER_OFF 0x02
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#define ACP3x_POWER_OFF_IN_PROGRESS 0x03
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#define ACP3x_SOFT_RESET__SoftResetAudDone_MASK 0x00010001
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#define ACP_SRAM_PTE_OFFSET 0x02050000
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#define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
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#define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
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#define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
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#define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
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#define PAGE_SIZE_4K_ENABLE 0x2
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#define I2S_SP_TX_MEM_WINDOW_START 0x4000000
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#define I2S_SP_RX_MEM_WINDOW_START 0x4020000
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#define I2S_BT_TX_MEM_WINDOW_START 0x4040000
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#define I2S_BT_RX_MEM_WINDOW_START 0x4060000
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#define SP_PB_FIFO_ADDR_OFFSET 0x500
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#define SP_CAPT_FIFO_ADDR_OFFSET 0x700
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#define BT_PB_FIFO_ADDR_OFFSET 0x900
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#define BT_CAPT_FIFO_ADDR_OFFSET 0xB00
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#define PLAYBACK_MIN_NUM_PERIODS 2
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#define PLAYBACK_MAX_NUM_PERIODS 8
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#define PLAYBACK_MAX_PERIOD_SIZE 8192
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#define PLAYBACK_MIN_PERIOD_SIZE 1024
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#define CAPTURE_MIN_NUM_PERIODS 2
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#define CAPTURE_MAX_NUM_PERIODS 8
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#define CAPTURE_MAX_PERIOD_SIZE 8192
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#define CAPTURE_MIN_PERIOD_SIZE 1024
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#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
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#define MIN_BUFFER MAX_BUFFER
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#define FIFO_SIZE 0x100
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#define DMA_SIZE 0x40
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#define FRM_LEN 0x100
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#define SLOT_WIDTH_8 0x08
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#define SLOT_WIDTH_16 0x10
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#define SLOT_WIDTH_24 0x18
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#define SLOT_WIDTH_32 0x20
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#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
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#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
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#define ACP_PGFSM_STATUS_MASK 0x03
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#define ACP_POWERED_ON 0x00
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#define ACP_POWER_ON_IN_PROGRESS 0x01
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#define ACP_POWERED_OFF 0x02
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#define ACP_POWER_OFF_IN_PROGRESS 0x03
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#define ACP3x_ITER_IRER_SAMP_LEN_MASK 0x38
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#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
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struct acp3x_platform_info {
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u16 play_i2s_instance;
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u16 cap_i2s_instance;
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u16 capture_channel;
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};
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struct i2s_dev_data {
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bool tdm_mode;
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unsigned int i2s_irq;
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u16 i2s_instance;
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u32 tdm_fmt;
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u32 substream_type;
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void __iomem *acp3x_base;
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struct snd_pcm_substream *play_stream;
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struct snd_pcm_substream *capture_stream;
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struct snd_pcm_substream *i2ssp_play_stream;
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struct snd_pcm_substream *i2ssp_capture_stream;
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};
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struct i2s_stream_instance {
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u16 num_pages;
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u16 i2s_instance;
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u16 capture_channel;
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u16 direction;
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u16 channels;
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u32 xfer_resolution;
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u32 val;
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dma_addr_t dma_addr;
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u64 bytescount;
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void __iomem *acp3x_base;
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};
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static inline u32 rv_readl(void __iomem *base_addr)
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{
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return readl(base_addr - ACP3x_PHY_BASE_ADDRESS);
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}
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static inline void rv_writel(u32 val, void __iomem *base_addr)
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{
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writel(val, base_addr - ACP3x_PHY_BASE_ADDRESS);
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}
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static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
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int direction)
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{
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u64 byte_count;
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if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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byte_count = rv_readl(rtd->acp3x_base +
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mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
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byte_count |= rv_readl(rtd->acp3x_base +
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mmACP_BT_TX_LINEARPOSITIONCNTR_LOW);
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break;
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case I2S_SP_INSTANCE:
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default:
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byte_count = rv_readl(rtd->acp3x_base +
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mmACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
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byte_count |= rv_readl(rtd->acp3x_base +
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mmACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
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}
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} else {
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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byte_count = rv_readl(rtd->acp3x_base +
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mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
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byte_count |= rv_readl(rtd->acp3x_base +
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mmACP_BT_RX_LINEARPOSITIONCNTR_LOW);
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break;
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case I2S_SP_INSTANCE:
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default:
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byte_count = rv_readl(rtd->acp3x_base +
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mmACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
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byte_count |= rv_readl(rtd->acp3x_base +
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mmACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
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}
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}
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return byte_count;
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}
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