/*
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*
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* Copyright (c) Fuzhou Rockchip Electronics Co.Ltd
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* Authors:
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* Mark Yao <yzq@rock-chips.com>
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*
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* base on exynos_drm.h
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _UAPI_ROCKCHIP_DRM_H
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#define _UAPI_ROCKCHIP_DRM_H
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#ifdef __KERNEL__
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#include <linux/types.h>
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#else
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#include <stdint.h>
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#endif
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#include <drm/drm.h>
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/*
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* Send vcnt event instead of blocking,
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* like _DRM_VBLANK_EVENT
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*/
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#define _DRM_ROCKCHIP_VCNT_EVENT 0x80000000
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#define DRM_EVENT_ROCKCHIP_CRTC_VCNT 0xf
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/* memory type definitions. */
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enum drm_rockchip_gem_mem_type {
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/* Physically Continuous memory. */
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ROCKCHIP_BO_CONTIG = 1 << 0,
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/* cachable mapping. */
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ROCKCHIP_BO_CACHABLE = 1 << 1,
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/* write-combine mapping. */
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ROCKCHIP_BO_WC = 1 << 2,
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ROCKCHIP_BO_SECURE = 1 << 3,
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/* keep kmap for cma buffer or alloc kmap for other type memory */
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ROCKCHIP_BO_ALLOC_KMAP = 1 << 4,
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/* alloc page with gfp_dma32 */
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ROCKCHIP_BO_DMA32 = 1 << 5,
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ROCKCHIP_BO_MASK = ROCKCHIP_BO_CONTIG | ROCKCHIP_BO_CACHABLE |
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ROCKCHIP_BO_WC | ROCKCHIP_BO_SECURE | ROCKCHIP_BO_ALLOC_KMAP |
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ROCKCHIP_BO_DMA32,
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};
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/**
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* User-desired buffer creation information structure.
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*
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* @size: user-desired memory allocation size.
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* @flags: user request for setting memory type or cache attributes.
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* @handle: returned a handle to created gem object.
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* - this handle will be set by gem module of kernel side.
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*/
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struct drm_rockchip_gem_create {
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uint64_t size;
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uint32_t flags;
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uint32_t handle;
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};
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struct drm_rockchip_gem_phys {
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uint32_t handle;
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uint32_t phy_addr;
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};
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/**
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* A structure for getting buffer offset.
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*
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* @handle: a pointer to gem object created.
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* @pad: just padding to be 64-bit aligned.
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* @offset: relatived offset value of the memory region allocated.
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* - this value should be set by user.
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*/
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struct drm_rockchip_gem_map_off {
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uint32_t handle;
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uint32_t pad;
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uint64_t offset;
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};
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/* acquire type definitions. */
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enum drm_rockchip_gem_cpu_acquire_type {
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DRM_ROCKCHIP_GEM_CPU_ACQUIRE_SHARED = 0x0,
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DRM_ROCKCHIP_GEM_CPU_ACQUIRE_EXCLUSIVE = 0x1,
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};
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enum rockchip_crtc_feture {
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ROCKCHIP_DRM_CRTC_FEATURE_ALPHA_SCALE,
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ROCKCHIP_DRM_CRTC_FEATURE_HDR10,
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ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR,
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};
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enum rockchip_plane_feture {
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ROCKCHIP_DRM_PLANE_FEATURE_SCALE,
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ROCKCHIP_DRM_PLANE_FEATURE_ALPHA,
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ROCKCHIP_DRM_PLANE_FEATURE_HDR2SDR,
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ROCKCHIP_DRM_PLANE_FEATURE_SDR2HDR,
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ROCKCHIP_DRM_PLANE_FEATURE_AFBDC,
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ROCKCHIP_DRM_PLANE_FEATURE_PDAF_POS,
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ROCKCHIP_DRM_PLANE_FEATURE_MAX,
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};
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enum rockchip_cabc_mode {
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ROCKCHIP_DRM_CABC_MODE_DISABLE,
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ROCKCHIP_DRM_CABC_MODE_NORMAL,
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ROCKCHIP_DRM_CABC_MODE_LOWPOWER,
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ROCKCHIP_DRM_CABC_MODE_USERSPACE,
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};
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#define DRM_ROCKCHIP_GEM_CREATE 0x00
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#define DRM_ROCKCHIP_GEM_MAP_OFFSET 0x01
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#define DRM_ROCKCHIP_GEM_CPU_ACQUIRE 0x02
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#define DRM_ROCKCHIP_GEM_CPU_RELEASE 0x03
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#define DRM_ROCKCHIP_GEM_GET_PHYS 0x04
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#define DRM_ROCKCHIP_GET_VCNT_EVENT 0x05
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#define DRM_IOCTL_ROCKCHIP_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_GEM_CREATE, struct drm_rockchip_gem_create)
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#define DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_GEM_MAP_OFFSET, struct drm_rockchip_gem_map_off)
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#define DRM_IOCTL_ROCKCHIP_GEM_CPU_ACQUIRE DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_GEM_CPU_ACQUIRE, struct drm_rockchip_gem_cpu_acquire)
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#define DRM_IOCTL_ROCKCHIP_GEM_CPU_RELEASE DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_GEM_CPU_RELEASE, struct drm_rockchip_gem_cpu_release)
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#define DRM_IOCTL_ROCKCHIP_GEM_GET_PHYS DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_GEM_GET_PHYS, struct drm_rockchip_gem_phys)
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#define DRM_IOCTL_ROCKCHIP_GET_VCNT_EVENT DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_GET_VCNT_EVENT, union drm_wait_vblank)
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#endif /* _UAPI_ROCKCHIP_DRM_H */
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