/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _RGA_DRIVER_H_
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#define _RGA_DRIVER_H_
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#include <linux/mutex.h>
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#include <linux/scatterlist.h>
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#define RGA_BLIT_SYNC 0x5017
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#define RGA_BLIT_ASYNC 0x5018
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#define RGA_FLUSH 0x5019
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#define RGA_GET_RESULT 0x501a
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#define RGA_GET_VERSION 0x501b
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#define RGA_REG_CTRL_LEN 0x8 /* 8 */
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#define RGA_REG_CMD_LEN 0x20 /* 32 */
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#define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */
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#define RGA_OUT_OF_RESOURCES -10
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#define RGA_MALLOC_ERROR -11
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#define RGA_BUF_GEM_TYPE_MASK 0xC0
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#define rgaIS_ERROR(status) (status < 0)
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#define rgaNO_ERROR(status) (status >= 0)
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#define rgaIS_SUCCESS(status) (status == 0)
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#define RGA_DEBUGFS 1
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/* RGA process mode enum */
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enum
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{
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bitblt_mode = 0x0,
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color_palette_mode = 0x1,
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color_fill_mode = 0x2,
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line_point_drawing_mode = 0x3,
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blur_sharp_filter_mode = 0x4,
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pre_scaling_mode = 0x5,
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update_palette_table_mode = 0x6,
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update_patten_buff_mode = 0x7,
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};
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enum
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{
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rop_enable_mask = 0x2,
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dither_enable_mask = 0x8,
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fading_enable_mask = 0x10,
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PD_enbale_mask = 0x20,
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};
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enum
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{
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yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */
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yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */
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yuv2rgb_mode2 = 0x2, /* BT.709 */
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};
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/* RGA rotate mode */
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enum
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{
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rotate_mode0 = 0x0, /* no rotate */
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rotate_mode1 = 0x1, /* rotate */
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rotate_mode2 = 0x2, /* x_mirror */
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rotate_mode3 = 0x3, /* y_mirror */
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};
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enum
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{
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color_palette_mode0 = 0x0, /* 1K */
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color_palette_mode1 = 0x1, /* 2K */
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color_palette_mode2 = 0x2, /* 4K */
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color_palette_mode3 = 0x3, /* 8K */
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};
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/*
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// Alpha Red Green Blue
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{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888
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{ 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888
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{ 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888
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{ 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888
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{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565
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{ 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551
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{ 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444
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{ 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888
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*/
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enum
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{
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RK_FORMAT_RGBA_8888 = 0x0,
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RK_FORMAT_RGBX_8888 = 0x1,
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RK_FORMAT_RGB_888 = 0x2,
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RK_FORMAT_BGRA_8888 = 0x3,
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RK_FORMAT_RGB_565 = 0x4,
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RK_FORMAT_RGBA_5551 = 0x5,
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RK_FORMAT_RGBA_4444 = 0x6,
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RK_FORMAT_BGR_888 = 0x7,
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RK_FORMAT_YCbCr_422_SP = 0x8,
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RK_FORMAT_YCbCr_422_P = 0x9,
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RK_FORMAT_YCbCr_420_SP = 0xa,
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RK_FORMAT_YCbCr_420_P = 0xb,
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RK_FORMAT_YCrCb_422_SP = 0xc,
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RK_FORMAT_YCrCb_422_P = 0xd,
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RK_FORMAT_YCrCb_420_SP = 0xe,
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RK_FORMAT_YCrCb_420_P = 0xf,
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RK_FORMAT_BPP1 = 0x10,
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RK_FORMAT_BPP2 = 0x11,
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RK_FORMAT_BPP4 = 0x12,
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RK_FORMAT_BPP8 = 0x13,
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RK_FORMAT_YCbCr_420_SP_10B = 0x20,
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RK_FORMAT_YCrCb_420_SP_10B = 0x21,
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};
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typedef struct rga_img_info_t
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{
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unsigned long yrgb_addr; /* yrgb mem addr */
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unsigned long uv_addr; /* cb/cr mem addr */
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unsigned long v_addr; /* cr mem addr */
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unsigned int format; //definition by RK_FORMAT
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unsigned short act_w;
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unsigned short act_h;
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unsigned short x_offset;
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unsigned short y_offset;
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unsigned short vir_w;
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unsigned short vir_h;
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unsigned short endian_mode; //for BPP
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unsigned short alpha_swap;
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}
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rga_img_info_t;
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typedef struct mdp_img_act
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{
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unsigned short w; // width
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unsigned short h; // height
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short x_off; // x offset for the vir
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short y_off; // y offset for the vir
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}
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mdp_img_act;
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typedef struct RANGE
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{
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unsigned short min;
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unsigned short max;
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}
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RANGE;
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typedef struct POINT
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{
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unsigned short x;
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unsigned short y;
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}
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POINT;
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typedef struct RECT
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{
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unsigned short xmin;
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unsigned short xmax; // width - 1
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unsigned short ymin;
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unsigned short ymax; // height - 1
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} RECT;
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typedef struct RGB
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{
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unsigned char r;
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unsigned char g;
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unsigned char b;
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unsigned char res;
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}RGB;
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typedef struct MMU
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{
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unsigned char mmu_en;
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unsigned long base_addr;
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uint32_t mmu_flag;
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} MMU;
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typedef struct COLOR_FILL
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{
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short gr_x_a;
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short gr_y_a;
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short gr_x_b;
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short gr_y_b;
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short gr_x_g;
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short gr_y_g;
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short gr_x_r;
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short gr_y_r;
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//u8 cp_gr_saturation;
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}
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COLOR_FILL;
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typedef struct FADING
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{
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uint8_t b;
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uint8_t g;
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uint8_t r;
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uint8_t res;
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}
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FADING;
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typedef struct line_draw_t
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{
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POINT start_point; /* LineDraw_start_point */
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POINT end_point; /* LineDraw_end_point */
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uint32_t color; /* LineDraw_color */
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uint32_t flag; /* (enum) LineDrawing mode sel */
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uint32_t line_width; /* range 1~16 */
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}
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line_draw_t;
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struct rga_req {
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uint8_t render_mode; /* (enum) process mode sel */
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rga_img_info_t src; /* src image info */
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rga_img_info_t dst; /* dst image info */
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rga_img_info_t pat; /* patten image info */
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unsigned long rop_mask_addr; /* rop4 mask addr */
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unsigned long LUT_addr; /* LUT addr */
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RECT clip; /* dst clip window default value is dst_vir */
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/* value from [0, w-1] / [0, h-1]*/
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int32_t sina; /* dst angle default value 0 16.16 scan from table */
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int32_t cosa; /* dst angle default value 0 16.16 scan from table */
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uint16_t alpha_rop_flag; /* alpha rop process flag */
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/* ([0] = 1 alpha_rop_enable) */
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/* ([1] = 1 rop enable) */
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/* ([2] = 1 fading_enable) */
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/* ([3] = 1 PD_enable) */
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/* ([4] = 1 alpha cal_mode_sel) */
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/* ([5] = 1 dither_enable) */
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/* ([6] = 1 gradient fill mode sel) */
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/* ([7] = 1 AA_enable) */
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uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */
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uint32_t color_key_max; /* color key max */
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uint32_t color_key_min; /* color key min */
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uint32_t fg_color; /* foreground color */
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uint32_t bg_color; /* background color */
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COLOR_FILL gr_color; /* color fill use gradient */
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line_draw_t line_draw_info;
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FADING fading;
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uint8_t PD_mode; /* porter duff alpha mode sel */
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uint8_t alpha_global_value; /* global alpha value */
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uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/
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uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/
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uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
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uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
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uint8_t endian_mode; /* 0/big endian 1/little endian*/
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uint8_t rotate_mode; /* (enum) rotate mode */
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/* 0x0, no rotate */
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/* 0x1, rotate */
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/* 0x2, x_mirror */
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/* 0x3, y_mirror */
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uint8_t color_fill_mode; /* 0 solid color / 1 patten color */
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MMU mmu_info; /* mmu information */
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uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */
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/* ([2~3] rop mode) */
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/* ([4] zero mode en) */
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/* ([5] dst alpha mode) */
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uint8_t src_trans_mode;
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struct sg_table *sg_src;
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struct sg_table *sg_dst;
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struct dma_buf_attachment *attach_src;
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struct dma_buf_attachment *attach_dst;
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};
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typedef struct TILE_INFO
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{
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int64_t matrix[4];
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uint16_t tile_x_num; /* x axis tile num / tile size is 8x8 pixel */
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uint16_t tile_y_num; /* y axis tile num */
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int16_t dst_x_tmp; /* dst pos x = (xstart - xoff) default value 0 */
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int16_t dst_y_tmp; /* dst pos y = (ystart - yoff) default value 0 */
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uint16_t tile_w;
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uint16_t tile_h;
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int16_t tile_start_x_coor;
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int16_t tile_start_y_coor;
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int32_t tile_xoff;
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int32_t tile_yoff;
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int32_t tile_temp_xstart;
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int32_t tile_temp_ystart;
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/* src tile incr */
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int32_t x_dx;
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int32_t x_dy;
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int32_t y_dx;
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int32_t y_dy;
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mdp_img_act dst_ctrl;
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}
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TILE_INFO;
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struct rga_mmu_buf_t {
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int32_t front;
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int32_t back;
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int32_t size;
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int32_t curr;
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unsigned int *buf;
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unsigned int *buf_virtual;
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struct page **pages;
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};
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/**
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* struct for process session which connect to rga
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*
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* @author ZhangShengqin (2012-2-15)
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*/
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typedef struct rga_session {
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/* a linked list of data so we can access them for debugging */
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struct list_head list_session;
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/* a linked list of register data waiting for process */
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struct list_head waiting;
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/* a linked list of register data in processing */
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struct list_head running;
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/* all coommand this thread done */
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atomic_t done;
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wait_queue_head_t wait;
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pid_t pid;
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atomic_t task_running;
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atomic_t num_done;
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} rga_session;
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struct rga_reg {
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rga_session *session;
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struct list_head session_link; /* link to rga service session */
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struct list_head status_link; /* link to register set list */
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uint32_t sys_reg[RGA_REG_CTRL_LEN];
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uint32_t cmd_reg[RGA_REG_CMD_LEN];
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uint32_t *MMU_base;
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uint32_t MMU_len;
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//atomic_t int_enable;
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//struct rga_req req;
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struct sg_table *sg_src;
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struct sg_table *sg_dst;
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struct dma_buf_attachment *attach_src;
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struct dma_buf_attachment *attach_dst;
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};
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typedef struct rga_service_info {
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struct mutex lock;
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struct timer_list timer; /* timer for power off */
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struct list_head waiting; /* link to link_reg in struct vpu_reg */
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struct list_head running; /* link to link_reg in struct vpu_reg */
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struct list_head done; /* link to link_reg in struct vpu_reg */
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struct list_head session; /* link to list_session in struct vpu_session */
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atomic_t total_running;
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struct rga_reg *reg;
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uint32_t cmd_buff[28*8];/* cmd_buff for rga */
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uint32_t *pre_scale_buf;
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atomic_t int_disable; /* 0 int enable 1 int disable */
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atomic_t cmd_num;
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atomic_t src_format_swt;
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int last_prc_src_format;
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atomic_t rga_working;
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bool enable;
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u32 dev_mode;
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//struct rga_req req[10];
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struct mutex mutex; // mutex
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} rga_service_info;
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#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026) || defined(CONFIG_ARCH_RK312x)
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#define RGA_BASE 0x1010c000
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#elif defined(CONFIG_ARCH_RK30)
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#define RGA_BASE 0x10114000
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#endif
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//General Registers
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#define RGA_SYS_CTRL 0x000
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#define RGA_CMD_CTRL 0x004
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#define RGA_CMD_ADDR 0x008
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#define RGA_STATUS 0x00c
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#define RGA_INT 0x010
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#define RGA_AXI_ID 0x014
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#define RGA_MMU_STA_CTRL 0x018
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#define RGA_MMU_STA 0x01c
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#define RGA_VERSION 0x028
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//Command code start
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#define RGA_MODE_CTRL 0x100
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//Source Image Registers
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#define RGA_SRC_Y_MST 0x104
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#define RGA_SRC_CB_MST 0x108
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#define RGA_MASK_READ_MST 0x108 //repeat
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#define RGA_SRC_CR_MST 0x10c
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#define RGA_SRC_VIR_INFO 0x110
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#define RGA_SRC_ACT_INFO 0x114
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#define RGA_SRC_X_PARA 0x118
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#define RGA_SRC_Y_PARA 0x11c
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#define RGA_SRC_TILE_XINFO 0x120
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#define RGA_SRC_TILE_YINFO 0x124
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#define RGA_SRC_TILE_H_INCR 0x128
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#define RGA_SRC_TILE_V_INCR 0x12c
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#define RGA_SRC_TILE_OFFSETX 0x130
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#define RGA_SRC_TILE_OFFSETY 0x134
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#define RGA_SRC_BG_COLOR 0x138
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#define RGA_SRC_FG_COLOR 0x13c
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#define RGA_LINE_DRAWING_COLOR 0x13c //repeat
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#define RGA_SRC_TR_COLOR0 0x140
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#define RGA_CP_GR_A 0x140 //repeat
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#define RGA_SRC_TR_COLOR1 0x144
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#define RGA_CP_GR_B 0x144 //repeat
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#define RGA_LINE_DRAW 0x148
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#define RGA_PAT_START_POINT 0x148 //repeat
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//Destination Image Registers
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#define RGA_DST_MST 0x14c
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#define RGA_LUT_MST 0x14c //repeat
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#define RGA_PAT_MST 0x14c //repeat
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#define RGA_LINE_DRAWING_MST 0x14c //repeat
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#define RGA_DST_VIR_INFO 0x150
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#define RGA_DST_CTR_INFO 0x154
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#define RGA_LINE_DRAW_XY_INFO 0x154 //repeat
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//Alpha/ROP Registers
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#define RGA_ALPHA_CON 0x158
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#define RGA_PAT_CON 0x15c
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#define RGA_DST_VIR_WIDTH_PIX 0x15c //repeat
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#define RGA_ROP_CON0 0x160
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#define RGA_CP_GR_G 0x160 //repeat
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#define RGA_PRESCL_CB_MST 0x160 //repeat
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#define RGA_ROP_CON1 0x164
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#define RGA_CP_GR_R 0x164 //repeat
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#define RGA_PRESCL_CR_MST 0x164 //repeat
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//MMU Register
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#define RGA_FADING_CON 0x168
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#define RGA_MMU_CTRL 0x168 //repeat
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#define RGA_MMU_TBL 0x16c //repeat
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#define RGA_YUV_OUT_CFG 0x170
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#define RGA_DST_UV_MST 0x174
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#define RGA_BLIT_COMPLETE_EVENT 1
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long rga_ioctl_kernel(struct rga_req *req);
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#endif /*_RK29_IPP_DRIVER_H_*/
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