/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd
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*
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* author:
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* Herman Chen <herman.chen@rock-chips.com>
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*/
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#ifndef __ROCKCHIP_MPP_RKVDEC2_LINK_H__
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#define __ROCKCHIP_MPP_RKVDEC2_LINK_H__
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#include "mpp_rkvdec2.h"
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#define RKVDEC_REG_IMPORTANT_BASE 0x2c
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#define RKVDEC_REG_IMPORTANT_INDEX 11
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#define RKVDEC_SOFTREST_EN BIT(20)
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#define RKVDEC_REG_SECOND_EN_BASE 0x30
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#define RKVDEC_REG_SECOND_EN_INDEX 12
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#define RKVDEC_WAIT_RESET_EN BIT(7)
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#define RKVDEC_REG_EN_MODE_SET 13
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#define RKVDEC_REG_DEBUG_INT_BASE 0x440
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#define RKVDEC_REG_DEBUG_INT_INDEX 272
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#define RKVDEC_BIT_BUS_IDLE BIT(0)
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#define RKVDEC_REG_TIMEOUT_THRESHOLD 32
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/* define for link hardware */
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#define RKVDEC_LINK_ADD_CFG_NUM 1
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#define RKVDEC_LINK_IRQ_BASE 0x000
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#define RKVDEC_LINK_BIT_IRQ_DIS BIT(2)
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#define RKVDEC_LINK_BIT_IRQ BIT(8)
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#define RKVDEC_LINK_BIT_IRQ_RAW BIT(9)
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#define RKVDEC_LINK_BIT_CORE_WORK_MODE BIT(16)
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#define RKVDEC_LINK_BIT_CCU_WORK_MODE BIT(17)
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#define RKVDEC_LINK_CFG_ADDR_BASE 0x004
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#define RKVDEC_LINK_MODE_BASE 0x008
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#define RKVDEC_LINK_BIT_ADD_MODE BIT(31)
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#define RKVDEC_LINK_CFG_CTRL_BASE 0x00c
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#define RKVDEC_LINK_BIT_CFG_DONE BIT(0)
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#define RKVDEC_LINK_DEC_NUM_BASE 0x010
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#define RKVDEC_LINK_TOTAL_NUM_BASE 0x014
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#define RKVDEC_LINK_EN_BASE 0x018
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#define RKVDEC_LINK_BIT_EN BIT(0)
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#define RKVDEC_LINK_NEXT_ADDR_BASE 0x01c
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#define RKVDEC_LINK_STA_BASE 0x024
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#define RKVDEC_LINK_REG_CYCLE_CNT 179
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/* define for ccu link hardware */
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#define RKVDEC_CCU_CTRL_BASE 0x000
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#define RKVDEC_CCU_BIT_AUTOGATE BIT(0)
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#define RKVDEC_CCU_BIT_FIX_RCB BIT(20)
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#define RKVDEC_CCU_CFG_ADDR_BASE 0x004
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#define RKVDEC_CCU_LINK_MODE_BASE 0x008
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#define RKVDEC_CCU_BIT_ADD_MODE BIT(31)
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#define RKVDEC_CCU_CFG_DONE_BASE 0x00c
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#define RKVDEC_CCU_BIT_CFG_DONE BIT(0)
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#define RKVDEC_CCU_DEC_NUM_BASE 0x010
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#define RKVDEC_CCU_TOTAL_NUM_BASE 0x014
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#define RKVDEC_CCU_WORK_BASE 0x018
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#define RKVDEC_CCU_BIT_WORK_EN BIT(0)
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#define RKVDEC_CCU_SEND_NUM_BASE 0x024
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#define RKVDEC_CCU_WORK_MODE_BASE 0x040
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#define RKVDEC_CCU_BIT_WORK_MODE BIT(0)
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#define RKVDEC_CCU_CORE_WORK_BASE 0x044
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#define RKVDEC_CCU_CORE_STA_BASE 0x048
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#define RKVDEC_CCU_CORE_IDLE_BASE 0x04c
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#define RKVDEC_CCU_CORE_ERR_BASE 0x054
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#define RKVDEC_CCU_CORE_RW_MASK 0x30000
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#define RKVDEC_MAX_WRITE_PART 6
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#define RKVDEC_MAX_READ_PART 2
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struct rkvdec_link_part {
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/* register offset of table buffer */
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u32 tb_reg_off;
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/* start idx of task register */
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u32 reg_start;
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/* number of task register */
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u32 reg_num;
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};
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struct rkvdec_link_status {
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u32 dec_num_mask;
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u32 err_flag_base;
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u32 err_flag_bit;
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};
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struct rkvdec_link_info {
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dma_addr_t iova;
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/* total register for link table buffer */
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u32 tb_reg_num;
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/* next link table addr in table buffer */
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u32 tb_reg_next;
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/* current read back addr in table buffer */
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u32 tb_reg_r;
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/* secondary enable in table buffer */
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u32 tb_reg_second_en;
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u32 part_w_num;
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u32 part_r_num;
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struct rkvdec_link_part part_w[RKVDEC_MAX_WRITE_PART];
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struct rkvdec_link_part part_r[RKVDEC_MAX_READ_PART];
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/* interrupt read back in table buffer */
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u32 tb_reg_int;
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u32 tb_reg_cycle;
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bool hack_setup;
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struct rkvdec_link_status reg_status;
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};
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struct rkvdec_link_dev {
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struct device *dev;
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struct mpp_dev *mpp;
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void __iomem *reg_base;
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u32 enabled;
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u32 link_mode;
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u32 decoded_status;
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u32 irq_status;
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u32 iova_curr;
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u32 iova_next;
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u32 decoded;
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u32 total;
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u32 error;
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u32 hack_task_running;
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struct rkvdec_link_info *info;
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struct mpp_dma_buffer *table;
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u32 link_node_size;
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u32 link_reg_count;
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/* taskqueue variables */
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u32 task_running;
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atomic_t task_pending;
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/* timeout can be trigger in different thread so atomic is needed */
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atomic_t task_timeout;
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u32 task_timeout_prev;
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/* link mode hardware status */
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atomic_t power_enabled;
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u32 irq_enabled;
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/* debug variable */
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u32 statistic_count;
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u64 task_cycle_sum;
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u32 task_cnt;
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u64 stuff_cycle_sum;
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u32 stuff_cnt;
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/* link info */
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u32 task_capacity;
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struct mpp_dma_buffer *table_array;
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struct list_head unused_list;
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struct list_head used_list;
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};
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enum RKVDEC2_CCU_MODE {
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RKVDEC2_CCU_MODE_NULL = 0,
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RKVDEC2_CCU_TASK_SOFT = 1,
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RKVDEC2_CCU_TASK_HARD = 2,
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RKVDEC2_CCU_MODE_BUTT,
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};
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struct rkvdec2_ccu {
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struct device *dev;
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/* register base */
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void __iomem *reg_base;
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atomic_t power_enabled;
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struct mpp_clk_info aclk_info;
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#ifdef CONFIG_ROCKCHIP_MPP_PROC_FS
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struct proc_dir_entry *procfs;
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#endif
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struct reset_control *rst_a;
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enum RKVDEC2_CCU_MODE ccu_mode;
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u32 ccu_core_work_mode;
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struct mpp_dma_buffer *table_array;
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struct list_head unused_list;
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struct list_head used_list;
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u32 timeout_flag;
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};
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extern struct rkvdec_link_info rkvdec_link_rk356x_hw_info;
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extern struct rkvdec_link_info rkvdec_link_v2_hw_info;
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extern struct rkvdec_link_info rkvdec_link_vdpu382_hw_info;
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int rkvdec_link_dump(struct mpp_dev *mpp);
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int rkvdec2_link_init(struct platform_device *pdev, struct rkvdec2_dev *dec);
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int rkvdec2_link_procfs_init(struct mpp_dev *mpp);
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int rkvdec2_link_remove(struct mpp_dev *mpp, struct rkvdec_link_dev *link_dec);
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irqreturn_t rkvdec2_link_irq_proc(int irq, void *param);
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int rkvdec2_link_process_task(struct mpp_session *session,
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struct mpp_task_msgs *msgs);
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int rkvdec2_link_wait_result(struct mpp_session *session,
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struct mpp_task_msgs *msgs);
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void rkvdec2_link_worker(struct kthread_work *work_s);
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void rkvdec2_link_session_deinit(struct mpp_session *session);
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/* for ccu link */
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int rkvdec2_attach_ccu(struct device *dev, struct rkvdec2_dev *dec);
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int rkvdec2_ccu_link_init(struct platform_device *pdev, struct rkvdec2_dev *dec);
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void *rkvdec2_ccu_alloc_task(struct mpp_session *session, struct mpp_task_msgs *msgs);
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int rkvdec2_ccu_iommu_fault_handle(struct iommu_domain *iommu,
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struct device *iommu_dev,
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unsigned long iova, int status, void *arg);
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irqreturn_t rkvdec2_soft_ccu_irq(int irq, void *param);
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void rkvdec2_soft_ccu_worker(struct kthread_work *work_s);
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int rkvdec2_ccu_alloc_table(struct rkvdec2_dev *dec,
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struct rkvdec_link_dev *link_dec);
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irqreturn_t rkvdec2_hard_ccu_irq(int irq, void *param);
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void rkvdec2_hard_ccu_worker(struct kthread_work *work_s);
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#endif
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