// SPDX-License-Identifier: GPL-2.0
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/*
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* Support for Intel Camera Imaging ISP subsystem.
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* Copyright (c) 2010 - 2015, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "hmm.h"
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#include "ia_css_types.h"
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#define __INLINE_SP__
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#include "sp.h"
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#include "assert_support.h"
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#include "ia_css_spctrl.h"
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#include "ia_css_debug.h"
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struct spctrl_context_info {
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struct ia_css_sp_init_dmem_cfg dmem_config;
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u32 spctrl_config_dmem_addr; /* location of dmem_cfg in SP dmem */
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u32 spctrl_state_dmem_addr;
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unsigned int sp_entry; /* entry function ptr on SP */
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ia_css_ptr code_addr; /* sp firmware location in host mem-DDR*/
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u32 code_size;
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char *program_name; /* used in case of PLATFORM_SIM */
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};
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static struct spctrl_context_info spctrl_cofig_info[N_SP_ID];
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static bool spctrl_loaded[N_SP_ID] = {0};
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/* Load firmware */
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int ia_css_spctrl_load_fw(sp_ID_t sp_id,
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ia_css_spctrl_cfg *spctrl_cfg)
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{
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ia_css_ptr code_addr = mmgr_NULL;
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struct ia_css_sp_init_dmem_cfg *init_dmem_cfg;
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if ((sp_id >= N_SP_ID) || (!spctrl_cfg))
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return -EINVAL;
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spctrl_cofig_info[sp_id].code_addr = mmgr_NULL;
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init_dmem_cfg = &spctrl_cofig_info[sp_id].dmem_config;
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init_dmem_cfg->dmem_data_addr = spctrl_cfg->dmem_data_addr;
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init_dmem_cfg->dmem_bss_addr = spctrl_cfg->dmem_bss_addr;
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init_dmem_cfg->data_size = spctrl_cfg->data_size;
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init_dmem_cfg->bss_size = spctrl_cfg->bss_size;
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init_dmem_cfg->sp_id = sp_id;
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spctrl_cofig_info[sp_id].spctrl_config_dmem_addr =
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spctrl_cfg->spctrl_config_dmem_addr;
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spctrl_cofig_info[sp_id].spctrl_state_dmem_addr =
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spctrl_cfg->spctrl_state_dmem_addr;
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/* store code (text + icache) and data to DDR
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*
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* Data used to be stored separately, because of access alignment constraints,
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* fix the FW generation instead
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*/
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code_addr = hmm_alloc(spctrl_cfg->code_size, HMM_BO_PRIVATE, 0, NULL, 0);
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if (code_addr == mmgr_NULL)
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return -ENOMEM;
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hmm_store(code_addr, spctrl_cfg->code, spctrl_cfg->code_size);
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if (sizeof(ia_css_ptr) > sizeof(hrt_data)) {
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ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
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"size of ia_css_ptr can not be greater than hrt_data\n");
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hmm_free(code_addr);
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code_addr = mmgr_NULL;
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return -EINVAL;
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}
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init_dmem_cfg->ddr_data_addr = code_addr + spctrl_cfg->ddr_data_offset;
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if ((init_dmem_cfg->ddr_data_addr % HIVE_ISP_DDR_WORD_BYTES) != 0) {
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ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
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"DDR address pointer is not properly aligned for DMA transfer\n");
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hmm_free(code_addr);
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code_addr = mmgr_NULL;
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return -EINVAL;
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}
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spctrl_cofig_info[sp_id].sp_entry = spctrl_cfg->sp_entry;
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spctrl_cofig_info[sp_id].code_addr = code_addr;
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spctrl_cofig_info[sp_id].program_name = spctrl_cfg->program_name;
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/* now we program the base address into the icache and
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* invalidate the cache.
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*/
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sp_ctrl_store(sp_id, SP_ICACHE_ADDR_REG,
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(hrt_data)spctrl_cofig_info[sp_id].code_addr);
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sp_ctrl_setbit(sp_id, SP_ICACHE_INV_REG, SP_ICACHE_INV_BIT);
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spctrl_loaded[sp_id] = true;
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return 0;
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}
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/* ISP2401 */
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/* reload pre-loaded FW */
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void sh_css_spctrl_reload_fw(sp_ID_t sp_id)
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{
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/* now we program the base address into the icache and
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* invalidate the cache.
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*/
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sp_ctrl_store(sp_id, SP_ICACHE_ADDR_REG,
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(hrt_data)spctrl_cofig_info[sp_id].code_addr);
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sp_ctrl_setbit(sp_id, SP_ICACHE_INV_REG, SP_ICACHE_INV_BIT);
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spctrl_loaded[sp_id] = true;
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}
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ia_css_ptr get_sp_code_addr(sp_ID_t sp_id)
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{
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return spctrl_cofig_info[sp_id].code_addr;
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}
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int ia_css_spctrl_unload_fw(sp_ID_t sp_id)
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{
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if ((sp_id >= N_SP_ID) || ((sp_id < N_SP_ID) && (!spctrl_loaded[sp_id])))
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return -EINVAL;
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/* freeup the resource */
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if (spctrl_cofig_info[sp_id].code_addr) {
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hmm_free(spctrl_cofig_info[sp_id].code_addr);
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spctrl_cofig_info[sp_id].code_addr = mmgr_NULL;
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}
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spctrl_loaded[sp_id] = false;
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return 0;
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}
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/* Initialize dmem_cfg in SP dmem and start SP program*/
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int ia_css_spctrl_start(sp_ID_t sp_id)
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{
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if ((sp_id >= N_SP_ID) || ((sp_id < N_SP_ID) && (!spctrl_loaded[sp_id])))
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return -EINVAL;
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/* Set descr in the SP to initialize the SP DMEM */
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/*
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* The FW stores user-space pointers to the FW, the ISP pointer
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* is only available here
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*
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*/
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assert(sizeof(unsigned int) <= sizeof(hrt_data));
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sp_dmem_store(sp_id,
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spctrl_cofig_info[sp_id].spctrl_config_dmem_addr,
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&spctrl_cofig_info[sp_id].dmem_config,
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sizeof(spctrl_cofig_info[sp_id].dmem_config));
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/* set the start address */
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sp_ctrl_store(sp_id, SP_START_ADDR_REG,
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(hrt_data)spctrl_cofig_info[sp_id].sp_entry);
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sp_ctrl_setbit(sp_id, SP_SC_REG, SP_RUN_BIT);
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sp_ctrl_setbit(sp_id, SP_SC_REG, SP_START_BIT);
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return 0;
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}
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/* Query the state of SP1 */
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ia_css_spctrl_sp_sw_state ia_css_spctrl_get_state(sp_ID_t sp_id)
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{
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ia_css_spctrl_sp_sw_state state = 0;
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unsigned int HIVE_ADDR_sp_sw_state;
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if (sp_id >= N_SP_ID)
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return IA_CSS_SP_SW_TERMINATED;
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HIVE_ADDR_sp_sw_state = spctrl_cofig_info[sp_id].spctrl_state_dmem_addr;
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(void)HIVE_ADDR_sp_sw_state; /* Suppres warnings in CRUN */
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if (sp_id == SP0_ID)
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state = sp_dmem_load_uint32(sp_id, (unsigned int)sp_address_of(sp_sw_state));
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return state;
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}
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int ia_css_spctrl_is_idle(sp_ID_t sp_id)
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{
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int state = 0;
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assert(sp_id < N_SP_ID);
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state = sp_ctrl_getbit(sp_id, SP_SC_REG, SP_IDLE_BIT);
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return state;
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}
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