// SPDX-License-Identifier: GPL-2.0+
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/*
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* ni_6527.c
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* Comedi driver for National Instruments PCI-6527
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*
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* COMEDI - Linux Control and Measurement Device Interface
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* Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
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*/
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/*
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* Driver: ni_6527
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* Description: National Instruments 6527
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* Devices: [National Instruments] PCI-6527 (pci-6527), PXI-6527 (pxi-6527)
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* Author: David A. Schleef <ds@schleef.org>
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* Updated: Sat, 25 Jan 2003 13:24:40 -0800
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* Status: works
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*
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* Configuration Options: not applicable, uses PCI auto config
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include "../comedi_pci.h"
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/*
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* PCI BAR1 - Register memory map
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*
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* Manuals (available from ftp://ftp.natinst.com/support/manuals)
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* 370106b.pdf 6527 Register Level Programmer Manual
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*/
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#define NI6527_DI_REG(x) (0x00 + (x))
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#define NI6527_DO_REG(x) (0x03 + (x))
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#define NI6527_ID_REG 0x06
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#define NI6527_CLR_REG 0x07
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#define NI6527_CLR_EDGE BIT(3)
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#define NI6527_CLR_OVERFLOW BIT(2)
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#define NI6527_CLR_FILT BIT(1)
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#define NI6527_CLR_INTERVAL BIT(0)
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#define NI6527_CLR_IRQS (NI6527_CLR_EDGE | NI6527_CLR_OVERFLOW)
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#define NI6527_CLR_RESET_FILT (NI6527_CLR_FILT | NI6527_CLR_INTERVAL)
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#define NI6527_FILT_INTERVAL_REG(x) (0x08 + (x))
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#define NI6527_FILT_ENA_REG(x) (0x0c + (x))
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#define NI6527_STATUS_REG 0x14
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#define NI6527_STATUS_IRQ BIT(2)
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#define NI6527_STATUS_OVERFLOW BIT(1)
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#define NI6527_STATUS_EDGE BIT(0)
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#define NI6527_CTRL_REG 0x15
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#define NI6527_CTRL_FALLING BIT(4)
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#define NI6527_CTRL_RISING BIT(3)
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#define NI6527_CTRL_IRQ BIT(2)
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#define NI6527_CTRL_OVERFLOW BIT(1)
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#define NI6527_CTRL_EDGE BIT(0)
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#define NI6527_CTRL_DISABLE_IRQS 0
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#define NI6527_CTRL_ENABLE_IRQS (NI6527_CTRL_FALLING | \
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NI6527_CTRL_RISING | \
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NI6527_CTRL_IRQ | NI6527_CTRL_EDGE)
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#define NI6527_RISING_EDGE_REG(x) (0x18 + (x))
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#define NI6527_FALLING_EDGE_REG(x) (0x20 + (x))
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enum ni6527_boardid {
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BOARD_PCI6527,
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BOARD_PXI6527,
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};
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struct ni6527_board {
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const char *name;
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};
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static const struct ni6527_board ni6527_boards[] = {
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[BOARD_PCI6527] = {
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.name = "pci-6527",
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},
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[BOARD_PXI6527] = {
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.name = "pxi-6527",
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},
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};
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struct ni6527_private {
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unsigned int filter_interval;
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unsigned int filter_enable;
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};
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static void ni6527_set_filter_interval(struct comedi_device *dev,
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unsigned int val)
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{
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struct ni6527_private *devpriv = dev->private;
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if (val != devpriv->filter_interval) {
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writeb(val & 0xff, dev->mmio + NI6527_FILT_INTERVAL_REG(0));
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writeb((val >> 8) & 0xff,
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dev->mmio + NI6527_FILT_INTERVAL_REG(1));
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writeb((val >> 16) & 0x0f,
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dev->mmio + NI6527_FILT_INTERVAL_REG(2));
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writeb(NI6527_CLR_INTERVAL, dev->mmio + NI6527_CLR_REG);
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devpriv->filter_interval = val;
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}
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}
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static void ni6527_set_filter_enable(struct comedi_device *dev,
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unsigned int val)
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{
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writeb(val & 0xff, dev->mmio + NI6527_FILT_ENA_REG(0));
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writeb((val >> 8) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(1));
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writeb((val >> 16) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(2));
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}
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static int ni6527_di_insn_config(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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struct ni6527_private *devpriv = dev->private;
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unsigned int chan = CR_CHAN(insn->chanspec);
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unsigned int interval;
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switch (data[0]) {
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case INSN_CONFIG_FILTER:
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/*
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* The deglitch filter interval is specified in nanoseconds.
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* The hardware supports intervals in 200ns increments. Round
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* the user values up and return the actual interval.
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*/
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interval = (data[1] + 100) / 200;
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data[1] = interval * 200;
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if (interval) {
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ni6527_set_filter_interval(dev, interval);
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devpriv->filter_enable |= 1 << chan;
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} else {
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devpriv->filter_enable &= ~(1 << chan);
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}
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ni6527_set_filter_enable(dev, devpriv->filter_enable);
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break;
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default:
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return -EINVAL;
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}
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return insn->n;
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}
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static int ni6527_di_insn_bits(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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unsigned int val;
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val = readb(dev->mmio + NI6527_DI_REG(0));
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val |= (readb(dev->mmio + NI6527_DI_REG(1)) << 8);
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val |= (readb(dev->mmio + NI6527_DI_REG(2)) << 16);
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data[1] = val;
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return insn->n;
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}
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static int ni6527_do_insn_bits(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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unsigned int mask;
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mask = comedi_dio_update_state(s, data);
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if (mask) {
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/* Outputs are inverted */
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unsigned int val = s->state ^ 0xffffff;
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if (mask & 0x0000ff)
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writeb(val & 0xff, dev->mmio + NI6527_DO_REG(0));
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if (mask & 0x00ff00)
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writeb((val >> 8) & 0xff,
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dev->mmio + NI6527_DO_REG(1));
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if (mask & 0xff0000)
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writeb((val >> 16) & 0xff,
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dev->mmio + NI6527_DO_REG(2));
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}
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data[1] = s->state;
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return insn->n;
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}
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static irqreturn_t ni6527_interrupt(int irq, void *d)
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{
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struct comedi_device *dev = d;
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struct comedi_subdevice *s = dev->read_subdev;
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unsigned int status;
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status = readb(dev->mmio + NI6527_STATUS_REG);
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if (!(status & NI6527_STATUS_IRQ))
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return IRQ_NONE;
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if (status & NI6527_STATUS_EDGE) {
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comedi_buf_write_samples(s, &s->state, 1);
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comedi_handle_events(dev, s);
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}
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writeb(NI6527_CLR_IRQS, dev->mmio + NI6527_CLR_REG);
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return IRQ_HANDLED;
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}
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static int ni6527_intr_cmdtest(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_cmd *cmd)
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{
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int err = 0;
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/* Step 1 : check if triggers are trivially valid */
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err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
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err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
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err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
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err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
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err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
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if (err)
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return 1;
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/* Step 2a : make sure trigger sources are unique */
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/* Step 2b : and mutually compatible */
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/* Step 3: check if arguments are trivially valid */
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err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
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err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
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err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
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err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
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cmd->chanlist_len);
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err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
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if (err)
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return 3;
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/* Step 4: fix up any arguments */
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/* Step 5: check channel list if it exists */
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return 0;
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}
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static int ni6527_intr_cmd(struct comedi_device *dev,
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struct comedi_subdevice *s)
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{
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writeb(NI6527_CLR_IRQS, dev->mmio + NI6527_CLR_REG);
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writeb(NI6527_CTRL_ENABLE_IRQS, dev->mmio + NI6527_CTRL_REG);
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return 0;
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}
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static int ni6527_intr_cancel(struct comedi_device *dev,
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struct comedi_subdevice *s)
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{
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writeb(NI6527_CTRL_DISABLE_IRQS, dev->mmio + NI6527_CTRL_REG);
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return 0;
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}
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static int ni6527_intr_insn_bits(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn, unsigned int *data)
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{
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data[1] = 0;
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return insn->n;
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}
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static void ni6527_set_edge_detection(struct comedi_device *dev,
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unsigned int mask,
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unsigned int rising,
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unsigned int falling)
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{
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unsigned int i;
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rising &= mask;
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falling &= mask;
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for (i = 0; i < 2; i++) {
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if (mask & 0xff) {
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if (~mask & 0xff) {
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/* preserve rising-edge detection channels */
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rising |= readb(dev->mmio +
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NI6527_RISING_EDGE_REG(i)) &
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(~mask & 0xff);
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/* preserve falling-edge detection channels */
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falling |= readb(dev->mmio +
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NI6527_FALLING_EDGE_REG(i)) &
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(~mask & 0xff);
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}
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/* update rising-edge detection channels */
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writeb(rising & 0xff,
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dev->mmio + NI6527_RISING_EDGE_REG(i));
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/* update falling-edge detection channels */
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writeb(falling & 0xff,
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dev->mmio + NI6527_FALLING_EDGE_REG(i));
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}
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rising >>= 8;
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falling >>= 8;
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mask >>= 8;
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}
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}
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static int ni6527_intr_insn_config(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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unsigned int mask = 0xffffffff;
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unsigned int rising, falling, shift;
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switch (data[0]) {
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case INSN_CONFIG_CHANGE_NOTIFY:
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/* check_insn_config_length() does not check this instruction */
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if (insn->n != 3)
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return -EINVAL;
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rising = data[1];
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falling = data[2];
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ni6527_set_edge_detection(dev, mask, rising, falling);
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break;
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case INSN_CONFIG_DIGITAL_TRIG:
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/* check trigger number */
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if (data[1] != 0)
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return -EINVAL;
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/* check digital trigger operation */
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switch (data[2]) {
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case COMEDI_DIGITAL_TRIG_DISABLE:
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rising = 0;
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falling = 0;
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break;
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case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
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/* check shift amount */
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shift = data[3];
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if (shift >= 32) {
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mask = 0;
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rising = 0;
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falling = 0;
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} else {
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mask <<= shift;
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rising = data[4] << shift;
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falling = data[5] << shift;
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}
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break;
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default:
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return -EINVAL;
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}
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ni6527_set_edge_detection(dev, mask, rising, falling);
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break;
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default:
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return -EINVAL;
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}
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return insn->n;
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}
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static void ni6527_reset(struct comedi_device *dev)
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{
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/* disable deglitch filters on all channels */
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ni6527_set_filter_enable(dev, 0);
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/* disable edge detection */
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ni6527_set_edge_detection(dev, 0xffffffff, 0, 0);
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writeb(NI6527_CLR_IRQS | NI6527_CLR_RESET_FILT,
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dev->mmio + NI6527_CLR_REG);
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writeb(NI6527_CTRL_DISABLE_IRQS, dev->mmio + NI6527_CTRL_REG);
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}
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static int ni6527_auto_attach(struct comedi_device *dev,
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unsigned long context)
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{
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struct pci_dev *pcidev = comedi_to_pci_dev(dev);
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const struct ni6527_board *board = NULL;
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struct ni6527_private *devpriv;
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struct comedi_subdevice *s;
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int ret;
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if (context < ARRAY_SIZE(ni6527_boards))
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board = &ni6527_boards[context];
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if (!board)
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return -ENODEV;
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dev->board_ptr = board;
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dev->board_name = board->name;
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devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
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if (!devpriv)
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return -ENOMEM;
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ret = comedi_pci_enable(dev);
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if (ret)
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return ret;
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dev->mmio = pci_ioremap_bar(pcidev, 1);
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if (!dev->mmio)
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return -ENOMEM;
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/* make sure this is actually a 6527 device */
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if (readb(dev->mmio + NI6527_ID_REG) != 0x27)
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return -ENODEV;
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ni6527_reset(dev);
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ret = request_irq(pcidev->irq, ni6527_interrupt, IRQF_SHARED,
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dev->board_name, dev);
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if (ret == 0)
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dev->irq = pcidev->irq;
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ret = comedi_alloc_subdevices(dev, 3);
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if (ret)
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return ret;
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/* Digital Input subdevice */
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s = &dev->subdevices[0];
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s->type = COMEDI_SUBD_DI;
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s->subdev_flags = SDF_READABLE;
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s->n_chan = 24;
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s->maxdata = 1;
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s->range_table = &range_digital;
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s->insn_config = ni6527_di_insn_config;
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s->insn_bits = ni6527_di_insn_bits;
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/* Digital Output subdevice */
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s = &dev->subdevices[1];
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s->type = COMEDI_SUBD_DO;
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s->subdev_flags = SDF_WRITABLE;
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s->n_chan = 24;
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s->maxdata = 1;
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s->range_table = &range_digital;
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s->insn_bits = ni6527_do_insn_bits;
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/* Edge detection interrupt subdevice */
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s = &dev->subdevices[2];
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if (dev->irq) {
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dev->read_subdev = s;
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s->type = COMEDI_SUBD_DI;
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s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
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s->n_chan = 1;
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s->maxdata = 1;
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s->range_table = &range_digital;
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s->insn_config = ni6527_intr_insn_config;
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s->insn_bits = ni6527_intr_insn_bits;
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s->len_chanlist = 1;
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s->do_cmdtest = ni6527_intr_cmdtest;
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s->do_cmd = ni6527_intr_cmd;
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s->cancel = ni6527_intr_cancel;
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} else {
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s->type = COMEDI_SUBD_UNUSED;
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}
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return 0;
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}
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static void ni6527_detach(struct comedi_device *dev)
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{
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if (dev->mmio)
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ni6527_reset(dev);
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comedi_pci_detach(dev);
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}
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static struct comedi_driver ni6527_driver = {
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.driver_name = "ni_6527",
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.module = THIS_MODULE,
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.auto_attach = ni6527_auto_attach,
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.detach = ni6527_detach,
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};
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static int ni6527_pci_probe(struct pci_dev *dev,
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const struct pci_device_id *id)
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{
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return comedi_pci_auto_config(dev, &ni6527_driver, id->driver_data);
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}
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static const struct pci_device_id ni6527_pci_table[] = {
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{ PCI_VDEVICE(NI, 0x2b10), BOARD_PXI6527 },
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{ PCI_VDEVICE(NI, 0x2b20), BOARD_PCI6527 },
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{ 0 }
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};
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MODULE_DEVICE_TABLE(pci, ni6527_pci_table);
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static struct pci_driver ni6527_pci_driver = {
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.name = "ni_6527",
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.id_table = ni6527_pci_table,
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.probe = ni6527_pci_probe,
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.remove = comedi_pci_auto_unconfig,
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};
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module_comedi_pci_driver(ni6527_driver, ni6527_pci_driver);
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MODULE_AUTHOR("Comedi https://www.comedi.org");
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MODULE_DESCRIPTION("Comedi driver for National Instruments PCI-6527");
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MODULE_LICENSE("GPL");
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