// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip PVTM support.
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*
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* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
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* Author: Finley Xiao <finley.xiao@rock-chips.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/debugfs.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_clk.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/soc/rockchip/pvtm.h>
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#include <linux/thermal.h>
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#define wr_mask_bit(v, off, mask) ((v) << (off) | (mask) << (16 + off))
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#define PVTM(_id, _name, _num_rings, _start, _en, _cal, _done, _freq) \
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{ \
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.id = _id, \
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.name = _name, \
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.num_rings = _num_rings, \
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.bit_start = _start, \
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.bit_en = _en, \
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.reg_cal = _cal, \
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.bit_freq_done = _done, \
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.reg_freq = _freq, \
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}
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struct rockchip_pvtm;
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struct rockchip_pvtm_ops {
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u32 (*get_value)(struct rockchip_pvtm *pvtm, unsigned int ring_sel,
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unsigned int time_us);
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void (*set_ring_sel)(struct rockchip_pvtm *pvtm, unsigned int ring_sel);
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};
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struct rockchip_pvtm_info {
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u32 reg_cal;
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u32 reg_freq;
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unsigned char id;
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unsigned char *name;
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unsigned int num_rings;
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unsigned int bit_start;
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unsigned int bit_en;
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unsigned int bit_freq_done;
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};
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struct rockchip_pvtm_data {
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u32 con;
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u32 sta;
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unsigned int num_pvtms;
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const struct rockchip_pvtm_info *infos;
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const struct rockchip_pvtm_ops ops;
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};
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struct rockchip_pvtm {
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u32 con;
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u32 sta;
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struct list_head node;
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struct device *dev;
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struct regmap *grf;
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void __iomem *base;
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int num_clks;
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struct clk_bulk_data *clks;
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struct reset_control *rst;
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struct thermal_zone_device *tz;
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const struct rockchip_pvtm_info *info;
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const struct rockchip_pvtm_ops *ops;
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struct dentry *dentry;
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};
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static LIST_HEAD(pvtm_list);
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#ifdef CONFIG_DEBUG_FS
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static struct dentry *rockchip_pvtm_debugfs_root;
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static int pvtm_value_show(struct seq_file *s, void *data)
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{
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struct rockchip_pvtm *pvtm = (struct rockchip_pvtm *)s->private;
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u32 value;
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int i, ret, cur_temp;
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if (!pvtm || !pvtm->ops->get_value) {
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seq_puts(s, "unsupported\n");
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return 0;
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}
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if (pvtm->tz && pvtm->tz->ops && pvtm->tz->ops->get_temp) {
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ret = pvtm->tz->ops->get_temp(pvtm->tz, &cur_temp);
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if (ret)
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dev_err(pvtm->dev, "debug failed to get temp\n");
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else
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seq_printf(s, "temp: %d ", cur_temp);
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}
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seq_puts(s, "pvtm: ");
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for (i = 0; i < pvtm->info->num_rings; i++) {
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value = pvtm->ops->get_value(pvtm, i, 1000);
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seq_printf(s, "%d ", value);
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}
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seq_puts(s, "\n");
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return 0;
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}
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static int pvtm_value_open(struct inode *inode, struct file *file)
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{
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return single_open(file, pvtm_value_show, inode->i_private);
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}
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static const struct file_operations pvtm_value_fops = {
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.open = pvtm_value_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int rockchip_pvtm_debugfs_init(void)
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{
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rockchip_pvtm_debugfs_root = debugfs_create_dir("pvtm", NULL);
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if (IS_ERR_OR_NULL(rockchip_pvtm_debugfs_root)) {
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pr_err("Failed to create pvtm debug directory\n");
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rockchip_pvtm_debugfs_root = NULL;
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return -ENOMEM;
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}
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return 0;
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}
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static void rockchip_pvtm_debugfs_exit(void)
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{
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debugfs_remove_recursive(rockchip_pvtm_debugfs_root);
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}
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static int rockchip_pvtm_add_debugfs(struct rockchip_pvtm *pvtm)
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{
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struct dentry *d;
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if (!rockchip_pvtm_debugfs_root)
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return 0;
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pvtm->dentry = debugfs_create_dir(pvtm->info->name,
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rockchip_pvtm_debugfs_root);
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if (!pvtm->dentry) {
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dev_err(pvtm->dev, "failed to create pvtm %s debug dir\n",
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pvtm->info->name);
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return -ENOMEM;
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}
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d = debugfs_create_file("value", 0444, pvtm->dentry,
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(void *)pvtm, &pvtm_value_fops);
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if (!d) {
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dev_err(pvtm->dev, "failed to pvtm %s value node\n",
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pvtm->info->name);
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debugfs_remove_recursive(pvtm->dentry);
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return -ENOMEM;
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}
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return 0;
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}
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#else
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static inline int rockchip_pvtm_debugfs_init(void)
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{
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return 0;
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}
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static inline void rockchip_pvtm_debugfs_exit(void)
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{
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}
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static inline int rockchip_pvtm_add_debugfs(struct rockchip_pvtm *pvtm)
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{
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return 0;
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}
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#endif
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static int rockchip_pvtm_reset(struct rockchip_pvtm *pvtm)
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{
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int ret;
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ret = reset_control_assert(pvtm->rst);
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if (ret) {
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dev_err(pvtm->dev, "failed to assert pvtm %d\n", ret);
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return ret;
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}
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udelay(2);
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ret = reset_control_deassert(pvtm->rst);
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if (ret) {
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dev_err(pvtm->dev, "failed to deassert pvtm %d\n", ret);
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return ret;
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}
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return 0;
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}
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u32 rockchip_get_pvtm_value(unsigned int id, unsigned int ring_sel,
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unsigned int time_us)
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{
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struct rockchip_pvtm *p, *pvtm = NULL;
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if (list_empty(&pvtm_list)) {
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pr_err("pvtm list NULL\n");
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return -EINVAL;
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}
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list_for_each_entry(p, &pvtm_list, node) {
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if (p->info->id == id) {
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pvtm = p;
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break;
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}
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}
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if (!pvtm) {
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pr_err("invalid pvtm id %d\n", id);
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return -EINVAL;
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}
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if (ring_sel >= pvtm->info->num_rings) {
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pr_err("invalid pvtm ring %d\n", ring_sel);
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return -EINVAL;
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}
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return pvtm->ops->get_value(pvtm, ring_sel, time_us);
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}
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EXPORT_SYMBOL(rockchip_get_pvtm_value);
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static void rockchip_pvtm_delay(unsigned int delay)
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{
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unsigned int ms = delay / 1000;
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unsigned int us = delay % 1000;
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if (ms > 0) {
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if (ms < 20)
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us += ms * 1000;
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else
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msleep(ms);
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}
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if (us >= 10)
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usleep_range(us, us + 100);
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else
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udelay(us);
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}
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static void px30_pvtm_set_ring_sel(struct rockchip_pvtm *pvtm,
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unsigned int ring_sel)
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{
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unsigned int id = pvtm->info->id;
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regmap_write(pvtm->grf, pvtm->con,
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wr_mask_bit(ring_sel, (id * 0x4 + 0x2), 0x3));
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}
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static void rk1808_pvtm_set_ring_sel(struct rockchip_pvtm *pvtm,
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unsigned int ring_sel)
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{
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regmap_write(pvtm->grf, pvtm->con,
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wr_mask_bit(ring_sel, 0x2, 0x7));
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}
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static void rk3399_pvtm_set_ring_sel(struct rockchip_pvtm *pvtm,
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unsigned int ring_sel)
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{
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unsigned int id = pvtm->info->id;
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if (id == 1) {
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regmap_write(pvtm->grf, pvtm->con + 0x14,
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wr_mask_bit(ring_sel >> 0x3, 0, 0x1));
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ring_sel &= 0x3;
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}
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if (id != 4)
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regmap_write(pvtm->grf, pvtm->con,
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wr_mask_bit(ring_sel, (id * 0x4 + 0x2), 0x3));
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}
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static u32 rockchip_pvtm_get_value(struct rockchip_pvtm *pvtm,
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unsigned int ring_sel,
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unsigned int time_us)
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{
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const struct rockchip_pvtm_info *info = pvtm->info;
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unsigned int clk_cnt, check_cnt = 100;
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u32 sta, val = 0;
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int ret;
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ret = clk_bulk_prepare_enable(pvtm->num_clks, pvtm->clks);
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if (ret < 0) {
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dev_err(pvtm->dev, "failed to prepare/enable pvtm clks\n");
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return 0;
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}
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ret = rockchip_pvtm_reset(pvtm);
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if (ret) {
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dev_err(pvtm->dev, "failed to reset pvtm\n");
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goto disable_clks;
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}
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/* if last status is enabled, stop calculating cycles first*/
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regmap_read(pvtm->grf, pvtm->con, &sta);
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if (sta & BIT(info->bit_en))
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regmap_write(pvtm->grf, pvtm->con,
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wr_mask_bit(0, info->bit_start, 0x1));
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regmap_write(pvtm->grf, pvtm->con,
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wr_mask_bit(0x1, info->bit_en, 0x1));
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if (pvtm->ops->set_ring_sel)
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pvtm->ops->set_ring_sel(pvtm, ring_sel);
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/* clk = 24 Mhz, T = 1 / 24 us */
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clk_cnt = time_us * 24;
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regmap_write(pvtm->grf, pvtm->con + info->reg_cal, clk_cnt);
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regmap_write(pvtm->grf, pvtm->con,
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wr_mask_bit(0x1, info->bit_start, 0x1));
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rockchip_pvtm_delay(time_us);
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while (check_cnt) {
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regmap_read(pvtm->grf, pvtm->sta, &sta);
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if (sta & BIT(info->bit_freq_done))
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break;
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udelay(4);
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check_cnt--;
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}
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if (check_cnt) {
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regmap_read(pvtm->grf, pvtm->sta + info->reg_freq, &val);
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} else {
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dev_err(pvtm->dev, "wait pvtm_done timeout!\n");
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val = 0;
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}
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regmap_write(pvtm->grf, pvtm->con,
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wr_mask_bit(0, info->bit_start, 0x1));
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regmap_write(pvtm->grf, pvtm->con,
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wr_mask_bit(0, info->bit_en, 0x1));
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disable_clks:
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clk_bulk_disable_unprepare(pvtm->num_clks, pvtm->clks);
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return val;
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}
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static void rv1106_core_pvtm_set_ring_sel(struct rockchip_pvtm *pvtm,
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unsigned int ring_sel)
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{
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writel_relaxed(wr_mask_bit(ring_sel + 4, 0x2, 0x7), pvtm->base + pvtm->con);
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}
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static void rv1126_pvtm_set_ring_sel(struct rockchip_pvtm *pvtm,
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unsigned int ring_sel)
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{
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writel_relaxed(wr_mask_bit(ring_sel, 0x2, 0x7), pvtm->base + pvtm->con);
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}
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static u32 rv1126_pvtm_get_value(struct rockchip_pvtm *pvtm,
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unsigned int ring_sel,
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unsigned int time_us)
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{
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const struct rockchip_pvtm_info *info = pvtm->info;
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unsigned int clk_cnt, check_cnt = 100;
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u32 sta, val = 0;
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int ret;
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ret = clk_bulk_prepare_enable(pvtm->num_clks, pvtm->clks);
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if (ret < 0) {
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dev_err(pvtm->dev, "failed to prepare/enable pvtm clks\n");
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return 0;
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}
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ret = rockchip_pvtm_reset(pvtm);
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if (ret) {
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dev_err(pvtm->dev, "failed to reset pvtm\n");
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goto disable_clks;
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}
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/* if last status is enabled, stop calculating cycles first*/
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sta = readl_relaxed(pvtm->base + pvtm->con);
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if (sta & BIT(info->bit_en))
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writel_relaxed(wr_mask_bit(0, info->bit_start, 0x1),
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pvtm->base + pvtm->con);
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writel_relaxed(wr_mask_bit(0x1, info->bit_en, 0x1),
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pvtm->base + pvtm->con);
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if (pvtm->ops->set_ring_sel)
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pvtm->ops->set_ring_sel(pvtm, ring_sel);
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/* clk = 24 Mhz, T = 1 / 24 us */
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clk_cnt = time_us * 24;
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writel_relaxed(clk_cnt, pvtm->base + pvtm->con + info->reg_cal);
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writel_relaxed(wr_mask_bit(0x1, info->bit_start, 0x1),
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pvtm->base + pvtm->con);
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rockchip_pvtm_delay(time_us);
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while (check_cnt) {
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sta = readl_relaxed(pvtm->base + pvtm->sta);
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if (sta & BIT(info->bit_freq_done))
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break;
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udelay(4);
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check_cnt--;
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}
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if (check_cnt) {
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val = readl_relaxed(pvtm->base + pvtm->sta + info->reg_freq);
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} else {
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dev_err(pvtm->dev, "wait pvtm_done timeout!\n");
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val = 0;
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}
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writel_relaxed(wr_mask_bit(0, info->bit_start, 0x1),
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pvtm->base + pvtm->con);
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writel_relaxed(wr_mask_bit(0, info->bit_en, 0x1),
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pvtm->base + pvtm->con);
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disable_clks:
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clk_bulk_disable_unprepare(pvtm->num_clks, pvtm->clks);
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return val;
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}
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static const struct rockchip_pvtm_info px30_pvtm_infos[] = {
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PVTM(0, "core", 3, 0, 1, 0x4, 0, 0x4),
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};
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static const struct rockchip_pvtm_data px30_pvtm = {
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.con = 0x80,
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.sta = 0x88,
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.num_pvtms = ARRAY_SIZE(px30_pvtm_infos),
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.infos = px30_pvtm_infos,
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.ops = {
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.get_value = rockchip_pvtm_get_value,
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.set_ring_sel = px30_pvtm_set_ring_sel,
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},
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};
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static const struct rockchip_pvtm_info px30_pmupvtm_infos[] = {
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PVTM(1, "pmu", 1, 0, 1, 0x4, 0, 0x4),
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};
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static const struct rockchip_pvtm_data px30_pmupvtm = {
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.con = 0x180,
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.sta = 0x190,
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.num_pvtms = ARRAY_SIZE(px30_pmupvtm_infos),
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.infos = px30_pmupvtm_infos,
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.ops = {
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.get_value = rockchip_pvtm_get_value,
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},
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};
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static const struct rockchip_pvtm_info rk1808_pvtm_infos[] = {
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PVTM(0, "core", 5, 0, 1, 0x4, 0, 0x4),
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};
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static const struct rockchip_pvtm_data rk1808_pvtm = {
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.con = 0x80,
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.sta = 0x88,
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.num_pvtms = ARRAY_SIZE(rk1808_pvtm_infos),
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.infos = rk1808_pvtm_infos,
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.ops = {
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.get_value = rockchip_pvtm_get_value,
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.set_ring_sel = rk1808_pvtm_set_ring_sel,
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},
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};
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static const struct rockchip_pvtm_info rk1808_pmupvtm_infos[] = {
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PVTM(1, "pmu", 1, 0, 1, 0x4, 0, 0x4),
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};
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static const struct rockchip_pvtm_data rk1808_pmupvtm = {
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.con = 0x180,
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.sta = 0x190,
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.num_pvtms = ARRAY_SIZE(rk1808_pmupvtm_infos),
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.infos = rk1808_pmupvtm_infos,
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.ops = {
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.get_value = rockchip_pvtm_get_value,
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},
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};
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static const struct rockchip_pvtm_info rk1808_npupvtm_infos[] = {
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PVTM(2, "npu", 5, 0, 1, 0x4, 0, 0x4),
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};
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static const struct rockchip_pvtm_data rk1808_npupvtm = {
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.con = 0x780,
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.sta = 0x788,
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.num_pvtms = ARRAY_SIZE(rk1808_npupvtm_infos),
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.infos = rk1808_npupvtm_infos,
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.ops = {
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.get_value = rockchip_pvtm_get_value,
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.set_ring_sel = rk1808_pvtm_set_ring_sel,
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},
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};
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static const struct rockchip_pvtm_info rk3288_pvtm_infos[] = {
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PVTM(0, "core", 1, 0, 1, 0x4, 1, 0x4),
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PVTM(1, "gpu", 1, 8, 9, 0x8, 0, 0x8),
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};
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static const struct rockchip_pvtm_data rk3288_pvtm = {
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.con = 0x368,
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.sta = 0x374,
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.num_pvtms = ARRAY_SIZE(rk3288_pvtm_infos),
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.infos = rk3288_pvtm_infos,
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.ops = {
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.get_value = rockchip_pvtm_get_value,
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},
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};
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static const struct rockchip_pvtm_data rk3308_pmupvtm = {
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.con = 0x440,
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.sta = 0x448,
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.num_pvtms = ARRAY_SIZE(px30_pmupvtm_infos),
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.infos = px30_pmupvtm_infos,
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.ops = {
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.get_value = rockchip_pvtm_get_value,
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},
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};
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static const struct rockchip_pvtm_info rk3399_pvtm_infos[] = {
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PVTM(0, "core_l", 4, 0, 1, 0x4, 0, 0x4),
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PVTM(1, "core_b", 6, 4, 5, 0x8, 1, 0x8),
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PVTM(2, "ddr", 4, 8, 9, 0xc, 3, 0x10),
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PVTM(3, "gpu", 4, 12, 13, 0x10, 2, 0xc),
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};
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static const struct rockchip_pvtm_data rk3399_pvtm = {
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.con = 0xe600,
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.sta = 0xe620,
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.num_pvtms = ARRAY_SIZE(rk3399_pvtm_infos),
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.infos = rk3399_pvtm_infos,
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.ops = {
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.get_value = rockchip_pvtm_get_value,
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.set_ring_sel = rk3399_pvtm_set_ring_sel,
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},
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};
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static const struct rockchip_pvtm_info rk3399_pmupvtm_infos[] = {
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PVTM(4, "pmu", 1, 0, 1, 0x4, 0, 0x4),
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};
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static const struct rockchip_pvtm_data rk3399_pmupvtm = {
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.con = 0x240,
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.sta = 0x248,
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.num_pvtms = ARRAY_SIZE(rk3399_pmupvtm_infos),
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.infos = rk3399_pmupvtm_infos,
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.ops = {
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.get_value = rockchip_pvtm_get_value,
|
},
|
};
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static const struct rockchip_pvtm_info rk3568_corepvtm_infos[] = {
|
PVTM(0, "core", 7, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rk3568_corepvtm = {
|
.con = 0x4,
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.sta = 0x80,
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.num_pvtms = ARRAY_SIZE(rk3568_corepvtm_infos),
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.infos = rk3568_corepvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
.set_ring_sel = rv1126_pvtm_set_ring_sel,
|
},
|
};
|
|
static const struct rockchip_pvtm_info rk3568_gpupvtm_infos[] = {
|
PVTM(1, "gpu", 7, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rk3568_gpupvtm = {
|
.con = 0x4,
|
.sta = 0x80,
|
.num_pvtms = ARRAY_SIZE(rk3568_gpupvtm_infos),
|
.infos = rk3568_gpupvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
.set_ring_sel = rv1126_pvtm_set_ring_sel,
|
},
|
};
|
|
static const struct rockchip_pvtm_info rk3568_npupvtm_infos[] = {
|
PVTM(2, "npu", 7, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rk3568_npupvtm = {
|
.con = 0x4,
|
.sta = 0x80,
|
.num_pvtms = ARRAY_SIZE(rk3568_npupvtm_infos),
|
.infos = rk3568_npupvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
.set_ring_sel = rv1126_pvtm_set_ring_sel,
|
},
|
};
|
|
static const struct rockchip_pvtm_info rk3588_bigcore0_pvtm_infos[] = {
|
PVTM(0, "bigcore0", 7, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rk3588_bigcore0_pvtm = {
|
.con = 0x4,
|
.sta = 0x80,
|
.num_pvtms = ARRAY_SIZE(rk3588_bigcore0_pvtm_infos),
|
.infos = rk3588_bigcore0_pvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
.set_ring_sel = rv1126_pvtm_set_ring_sel,
|
},
|
};
|
|
static const struct rockchip_pvtm_info rk3588_bigcore1_pvtm_infos[] = {
|
PVTM(1, "bigcore1", 7, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rk3588_bigcore1_pvtm = {
|
.con = 0x4,
|
.sta = 0x80,
|
.num_pvtms = ARRAY_SIZE(rk3588_bigcore1_pvtm_infos),
|
.infos = rk3588_bigcore1_pvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
.set_ring_sel = rv1126_pvtm_set_ring_sel,
|
},
|
};
|
|
static const struct rockchip_pvtm_info rk3588_litcore_pvtm_infos[] = {
|
PVTM(2, "litcore", 7, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rk3588_litcore_pvtm = {
|
.con = 0x4,
|
.sta = 0x80,
|
.num_pvtms = ARRAY_SIZE(rk3588_litcore_pvtm_infos),
|
.infos = rk3588_litcore_pvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
.set_ring_sel = rv1126_pvtm_set_ring_sel,
|
},
|
};
|
|
static const struct rockchip_pvtm_info rk3588_npu_pvtm_infos[] = {
|
PVTM(3, "npu", 2, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rk3588_npu_pvtm = {
|
.con = 0x4,
|
.sta = 0x80,
|
.num_pvtms = ARRAY_SIZE(rk3588_npu_pvtm_infos),
|
.infos = rk3588_npu_pvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
.set_ring_sel = rv1126_pvtm_set_ring_sel,
|
},
|
};
|
|
static const struct rockchip_pvtm_info rk3588_gpu_pvtm_infos[] = {
|
PVTM(4, "gpu", 2, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rk3588_gpu_pvtm = {
|
.con = 0x4,
|
.sta = 0x80,
|
.num_pvtms = ARRAY_SIZE(rk3588_gpu_pvtm_infos),
|
.infos = rk3588_gpu_pvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
.set_ring_sel = rv1126_pvtm_set_ring_sel,
|
},
|
};
|
|
static const struct rockchip_pvtm_info rk3588_pmu_pvtm_infos[] = {
|
PVTM(5, "pmu", 1, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rk3588_pmu_pvtm = {
|
.con = 0x4,
|
.sta = 0x80,
|
.num_pvtms = ARRAY_SIZE(rk3588_pmu_pvtm_infos),
|
.infos = rk3588_pmu_pvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
},
|
};
|
|
static const struct rockchip_pvtm_info rv1106_corepvtm_infos[] = {
|
PVTM(0, "core", 2, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rv1106_corepvtm = {
|
.con = 0x4,
|
.sta = 0x80,
|
.num_pvtms = ARRAY_SIZE(rv1106_corepvtm_infos),
|
.infos = rv1106_corepvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
.set_ring_sel = rv1106_core_pvtm_set_ring_sel,
|
},
|
};
|
|
static const struct rockchip_pvtm_info rv1106_pmupvtm_infos[] = {
|
PVTM(1, "pmu", 1, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rv1106_pmupvtm = {
|
.con = 0x4,
|
.sta = 0x80,
|
.num_pvtms = ARRAY_SIZE(rv1106_pmupvtm_infos),
|
.infos = rv1106_pmupvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
},
|
};
|
|
static const struct rockchip_pvtm_info rv1126_cpupvtm_infos[] = {
|
PVTM(0, "cpu", 7, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rv1126_cpupvtm = {
|
.con = 0x4,
|
.sta = 0x80,
|
.num_pvtms = ARRAY_SIZE(rv1126_cpupvtm_infos),
|
.infos = rv1126_cpupvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
.set_ring_sel = rv1126_pvtm_set_ring_sel,
|
},
|
};
|
|
static const struct rockchip_pvtm_info rv1126_npupvtm_infos[] = {
|
PVTM(1, "npu", 7, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rv1126_npupvtm = {
|
.con = 0x4,
|
.sta = 0x80,
|
.num_pvtms = ARRAY_SIZE(rv1126_npupvtm_infos),
|
.infos = rv1126_npupvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
.set_ring_sel = rv1126_pvtm_set_ring_sel,
|
},
|
};
|
|
static const struct rockchip_pvtm_info rv1126_pmupvtm_infos[] = {
|
PVTM(2, "pmu", 1, 0, 1, 0x4, 0, 0x4),
|
};
|
|
static const struct rockchip_pvtm_data rv1126_pmupvtm = {
|
.con = 0x4,
|
.sta = 0x80,
|
.num_pvtms = ARRAY_SIZE(rv1126_pmupvtm_infos),
|
.infos = rv1126_pmupvtm_infos,
|
.ops = {
|
.get_value = rv1126_pvtm_get_value,
|
},
|
};
|
|
static const struct of_device_id rockchip_pvtm_match[] = {
|
#ifdef CONFIG_CPU_PX30
|
{
|
.compatible = "rockchip,px30-pvtm",
|
.data = (void *)&px30_pvtm,
|
},
|
{
|
.compatible = "rockchip,px30-pmu-pvtm",
|
.data = (void *)&px30_pmupvtm,
|
},
|
#endif
|
#ifdef CONFIG_CPU_RK1808
|
{
|
.compatible = "rockchip,rk1808-pvtm",
|
.data = (void *)&rk1808_pvtm,
|
},
|
{
|
.compatible = "rockchip,rk1808-pmu-pvtm",
|
.data = (void *)&rk1808_pmupvtm,
|
},
|
{
|
.compatible = "rockchip,rk1808-npu-pvtm",
|
.data = (void *)&rk1808_npupvtm,
|
},
|
#endif
|
#ifdef CONFIG_CPU_RK3288
|
{
|
.compatible = "rockchip,rk3288-pvtm",
|
.data = (void *)&rk3288_pvtm,
|
},
|
#endif
|
#ifdef CONFIG_CPU_RK3308
|
{
|
.compatible = "rockchip,rk3308-pvtm",
|
.data = (void *)&px30_pvtm,
|
},
|
{
|
.compatible = "rockchip,rk3308-pmu-pvtm",
|
.data = (void *)&rk3308_pmupvtm,
|
},
|
#endif
|
#ifdef CONFIG_CPU_RK3399
|
{
|
.compatible = "rockchip,rk3399-pvtm",
|
.data = (void *)&rk3399_pvtm,
|
},
|
{
|
.compatible = "rockchip,rk3399-pmu-pvtm",
|
.data = (void *)&rk3399_pmupvtm,
|
},
|
#endif
|
#ifdef CONFIG_CPU_RK3568
|
{
|
.compatible = "rockchip,rK3568-core-pvtm",
|
.data = (void *)&rk3568_corepvtm,
|
},
|
{
|
.compatible = "rockchip,rk3568-gpu-pvtm",
|
.data = (void *)&rk3568_gpupvtm,
|
},
|
{
|
.compatible = "rockchip,rk3568-npu-pvtm",
|
.data = (void *)&rk3568_npupvtm,
|
},
|
#endif
|
#ifdef CONFIG_CPU_RK3588
|
{
|
.compatible = "rockchip,rk3588-bigcore0-pvtm",
|
.data = (void *)&rk3588_bigcore0_pvtm,
|
},
|
{
|
.compatible = "rockchip,rk3588-bigcore1-pvtm",
|
.data = (void *)&rk3588_bigcore1_pvtm,
|
},
|
{
|
.compatible = "rockchip,rk3588-litcore-pvtm",
|
.data = (void *)&rk3588_litcore_pvtm,
|
},
|
{
|
.compatible = "rockchip,rk3588-gpu-pvtm",
|
.data = (void *)&rk3588_gpu_pvtm,
|
},
|
{
|
.compatible = "rockchip,rk3588-npu-pvtm",
|
.data = (void *)&rk3588_npu_pvtm,
|
},
|
{
|
.compatible = "rockchip,rk3588-pmu-pvtm",
|
.data = (void *)&rk3588_pmu_pvtm,
|
},
|
#endif
|
#ifdef CONFIG_CPU_RV1106
|
{
|
.compatible = "rockchip,rv1106-core-pvtm",
|
.data = (void *)&rv1106_corepvtm,
|
},
|
{
|
.compatible = "rockchip,rv1106-pmu-pvtm",
|
.data = (void *)&rv1106_pmupvtm,
|
},
|
#endif
|
#ifdef CONFIG_CPU_RV1126
|
{
|
.compatible = "rockchip,rv1126-cpu-pvtm",
|
.data = (void *)&rv1126_cpupvtm,
|
},
|
{
|
.compatible = "rockchip,rv1126-npu-pvtm",
|
.data = (void *)&rv1126_npupvtm,
|
},
|
{
|
.compatible = "rockchip,rv1126-pmu-pvtm",
|
.data = (void *)&rv1126_pmupvtm,
|
},
|
#endif
|
{ /* sentinel */ },
|
};
|
MODULE_DEVICE_TABLE(of, rockchip_pvtm_match);
|
|
static int rockchip_pvtm_get_index(const struct rockchip_pvtm_data *data,
|
u32 ch, u32 *index)
|
{
|
int i;
|
|
for (i = 0; i < data->num_pvtms; i++) {
|
if (ch == data->infos[i].id) {
|
*index = i;
|
return 0;
|
}
|
}
|
|
return -EINVAL;
|
}
|
|
static struct rockchip_pvtm *
|
rockchip_pvtm_init(struct device *dev, struct device_node *node,
|
const struct rockchip_pvtm_data *data,
|
struct regmap *grf, void __iomem *base)
|
{
|
struct rockchip_pvtm *pvtm;
|
const char *tz_name;
|
u32 id, index;
|
int i;
|
|
if (of_property_read_u32(node, "reg", &id)) {
|
dev_err(dev, "%s: failed to retrieve pvtm id\n", node->name);
|
return NULL;
|
}
|
if (rockchip_pvtm_get_index(data, id, &index)) {
|
dev_err(dev, "%s: invalid pvtm id %d\n", node->name, id);
|
return NULL;
|
}
|
|
pvtm = devm_kzalloc(dev, sizeof(*pvtm), GFP_KERNEL);
|
if (!pvtm)
|
return NULL;
|
|
pvtm->dev = dev;
|
pvtm->grf = grf;
|
pvtm->base = base;
|
pvtm->con = data->con;
|
pvtm->sta = data->sta;
|
pvtm->ops = &data->ops;
|
pvtm->info = &data->infos[index];
|
|
if (!of_property_read_string(node, "thermal-zone", &tz_name)) {
|
pvtm->tz = thermal_zone_get_zone_by_name(tz_name);
|
if (IS_ERR(pvtm->tz)) {
|
dev_err(pvtm->dev, "failed to retrieve pvtm_tz\n");
|
pvtm->tz = NULL;
|
}
|
}
|
|
pvtm->num_clks = of_clk_get_parent_count(node);
|
if (pvtm->num_clks <= 0) {
|
dev_err(dev, "%s: does not have clocks\n", node->name);
|
goto clk_num_err;
|
}
|
pvtm->clks = devm_kcalloc(dev, pvtm->num_clks, sizeof(*pvtm->clks),
|
GFP_KERNEL);
|
if (!pvtm->clks)
|
goto clk_num_err;
|
for (i = 0; i < pvtm->num_clks; i++) {
|
pvtm->clks[i].clk = of_clk_get(node, i);
|
if (IS_ERR(pvtm->clks[i].clk)) {
|
dev_err(dev, "%s: failed to get clk at index %d\n",
|
node->name, i);
|
goto clk_err;
|
}
|
}
|
|
pvtm->rst = devm_reset_control_array_get_optional_exclusive(dev);
|
if (IS_ERR(pvtm->rst))
|
dev_dbg(dev, "%s: failed to get reset\n", node->name);
|
|
rockchip_pvtm_add_debugfs(pvtm);
|
|
return pvtm;
|
|
clk_err:
|
while (--i >= 0)
|
clk_put(pvtm->clks[i].clk);
|
devm_kfree(dev, pvtm->clks);
|
clk_num_err:
|
devm_kfree(dev, pvtm);
|
|
return NULL;
|
}
|
|
static int rockchip_pvtm_probe(struct platform_device *pdev)
|
{
|
struct device *dev = &pdev->dev;
|
struct device_node *np = pdev->dev.of_node;
|
struct device_node *node;
|
const struct of_device_id *match;
|
struct rockchip_pvtm *pvtm;
|
struct regmap *grf = NULL;
|
void __iomem *base = NULL;
|
|
match = of_match_device(dev->driver->of_match_table, dev);
|
if (!match || !match->data) {
|
dev_err(dev, "missing pvtm data\n");
|
return -EINVAL;
|
}
|
|
if (dev->parent && dev->parent->of_node) {
|
grf = syscon_node_to_regmap(dev->parent->of_node);
|
if (IS_ERR(grf))
|
return PTR_ERR(grf);
|
} else {
|
base = devm_platform_ioremap_resource(pdev, 0);
|
if (IS_ERR(base))
|
return PTR_ERR(base);
|
}
|
|
for_each_available_child_of_node(np, node) {
|
pvtm = rockchip_pvtm_init(dev, node, match->data, grf, base);
|
if (!pvtm) {
|
dev_err(dev, "failed to handle node %s\n",
|
node->full_name);
|
continue;
|
}
|
list_add(&pvtm->node, &pvtm_list);
|
dev_info(dev, "%s probed\n", node->full_name);
|
}
|
|
return 0;
|
}
|
|
static struct platform_driver rockchip_pvtm_driver = {
|
.probe = rockchip_pvtm_probe,
|
.driver = {
|
.name = "rockchip-pvtm",
|
.of_match_table = rockchip_pvtm_match,
|
},
|
};
|
|
static int __init rockchip_pvtm_module_init(void)
|
{
|
rockchip_pvtm_debugfs_init();
|
|
return platform_driver_register(&rockchip_pvtm_driver);
|
}
|
module_init(rockchip_pvtm_module_init);
|
|
static void __exit rockchip_pvtm_module_exit(void)
|
{
|
rockchip_pvtm_debugfs_exit();
|
platform_driver_unregister(&rockchip_pvtm_driver);
|
}
|
module_exit(rockchip_pvtm_module_exit);
|
|
MODULE_DESCRIPTION("Rockchip PVTM driver");
|
MODULE_AUTHOR("Finley Xiao <finley.xiao@rock-chips.com>");
|
MODULE_LICENSE("GPL v2");
|
