/* SPDX-License-Identifier: BSD-3-Clause */
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/* Copyright 2020, NXP Semiconductors
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*/
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#ifndef _SJA1105_SGMII_H
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#define _SJA1105_SGMII_H
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#define SJA1105_SGMII_PORT 4
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/* DIGITAL_CONTROL_1 (address 1f8000h) */
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#define SJA1105_DC1 0x8000
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#define SJA1105_DC1_VS_RESET BIT(15)
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#define SJA1105_DC1_REMOTE_LOOPBACK BIT(14)
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#define SJA1105_DC1_EN_VSMMD1 BIT(13)
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#define SJA1105_DC1_POWER_SAVE BIT(11)
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#define SJA1105_DC1_CLOCK_STOP_EN BIT(10)
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#define SJA1105_DC1_MAC_AUTO_SW BIT(9)
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#define SJA1105_DC1_INIT BIT(8)
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#define SJA1105_DC1_TX_DISABLE BIT(4)
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#define SJA1105_DC1_AUTONEG_TIMER_OVRR BIT(3)
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#define SJA1105_DC1_BYP_POWERUP BIT(1)
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#define SJA1105_DC1_PHY_MODE_CONTROL BIT(0)
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/* DIGITAL_CONTROL_2 register (address 1f80E1h) */
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#define SJA1105_DC2 0x80e1
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#define SJA1105_DC2_TX_POL_INV_DISABLE BIT(4)
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#define SJA1105_DC2_RX_POL_INV BIT(0)
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/* DIGITAL_ERROR_CNT register (address 1f80E2h) */
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#define SJA1105_DEC 0x80e2
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#define SJA1105_DEC_ICG_EC_ENA BIT(4)
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#define SJA1105_DEC_CLEAR_ON_READ BIT(0)
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/* AUTONEG_CONTROL register (address 1f8001h) */
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#define SJA1105_AC 0x8001
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#define SJA1105_AC_MII_CONTROL BIT(8)
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#define SJA1105_AC_SGMII_LINK BIT(4)
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#define SJA1105_AC_PHY_MODE BIT(3)
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#define SJA1105_AC_AUTONEG_MODE(x) (((x) << 1) & GENMASK(2, 1))
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#define SJA1105_AC_AUTONEG_MODE_SGMII SJA1105_AC_AUTONEG_MODE(2)
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/* AUTONEG_INTR_STATUS register (address 1f8002h) */
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#define SJA1105_AIS 0x8002
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#define SJA1105_AIS_LINK_STATUS(x) (!!((x) & BIT(4)))
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#define SJA1105_AIS_SPEED(x) (((x) & GENMASK(3, 2)) >> 2)
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#define SJA1105_AIS_DUPLEX_MODE(x) (!!((x) & BIT(1)))
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#define SJA1105_AIS_COMPLETE(x) (!!((x) & BIT(0)))
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/* DEBUG_CONTROL register (address 1f8005h) */
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#define SJA1105_DC 0x8005
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#define SJA1105_DC_SUPPRESS_LOS BIT(4)
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#define SJA1105_DC_RESTART_SYNC BIT(0)
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#endif
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