/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
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/*
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* Northstar Plus switch SerDes/SGMII PHY definitions
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*
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* Copyright (C) 2018 Florian Fainelli <f.fainelli@gmail.com>
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*/
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#include <linux/phy.h>
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#include <linux/types.h>
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/* Non-standard page used to access SerDes PHY registers on NorthStar Plus */
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#define B53_SERDES_PAGE 0x16
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#define B53_SERDES_BLKADDR 0x3e
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#define B53_SERDES_LANE 0x3c
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#define B53_SERDES_ID0 0x20
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#define SERDES_ID0_MODEL_MASK 0x3f
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#define SERDES_ID0_REV_NUM_SHIFT 11
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#define SERDES_ID0_REV_NUM_MASK 0x7
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#define SERDES_ID0_REV_LETTER_SHIFT 14
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#define B53_SERDES_MII_REG(x) (0x20 + (x) * 2)
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#define B53_SERDES_DIGITAL_CONTROL(x) (0x1e + (x) * 2)
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#define B53_SERDES_DIGITAL_STATUS 0x28
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/* SERDES_DIGITAL_CONTROL1 */
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#define FIBER_MODE_1000X BIT(0)
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#define TBI_INTERFACE BIT(1)
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#define SIGNAL_DETECT_EN BIT(2)
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#define INVERT_SIGNAL_DETECT BIT(3)
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#define AUTODET_EN BIT(4)
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#define SGMII_MASTER_MODE BIT(5)
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#define DISABLE_DLL_PWRDOWN BIT(6)
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#define CRC_CHECKER_DIS BIT(7)
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#define COMMA_DET_EN BIT(8)
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#define ZERO_COMMA_DET_EN BIT(9)
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#define REMOTE_LOOPBACK BIT(10)
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#define SEL_RX_PKTS_FOR_CNTR BIT(11)
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#define MASTER_MDIO_PHY_SEL BIT(13)
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#define DISABLE_SIGNAL_DETECT_FLT BIT(14)
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/* SERDES_DIGITAL_CONTROL2 */
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#define EN_PARALLEL_DET BIT(0)
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#define DIS_FALSE_LINK BIT(1)
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#define FLT_FORCE_LINK BIT(2)
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#define EN_AUTONEG_ERR_TIMER BIT(3)
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#define DIS_REMOTE_FAULT_SENSING BIT(4)
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#define FORCE_XMIT_DATA BIT(5)
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#define AUTONEG_FAST_TIMERS BIT(6)
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#define DIS_CARRIER_EXTEND BIT(7)
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#define DIS_TRRR_GENERATION BIT(8)
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#define BYPASS_PCS_RX BIT(9)
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#define BYPASS_PCS_TX BIT(10)
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#define TEST_CNTR_EN BIT(11)
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#define TX_PACKET_SEQ_TEST BIT(12)
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#define TX_IDLE_JAM_SEQ_TEST BIT(13)
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#define CLR_BER_CNTR BIT(14)
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/* SERDES_DIGITAL_CONTROL3 */
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#define TX_FIFO_RST BIT(0)
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#define FIFO_ELAST_TX_RX_SHIFT 1
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#define FIFO_ELAST_TX_RX_5K 0
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#define FIFO_ELAST_TX_RX_10K 1
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#define FIFO_ELAST_TX_RX_13_5K 2
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#define FIFO_ELAST_TX_RX_18_5K 3
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#define BLOCK_TXEN_MODE BIT(9)
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#define JAM_FALSE_CARRIER_MODE BIT(10)
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#define EXT_PHY_CRS_MODE BIT(11)
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#define INVERT_EXT_PHY_CRS BIT(12)
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#define DISABLE_TX_CRS BIT(13)
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/* SERDES_DIGITAL_STATUS */
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#define SGMII_MODE BIT(0)
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#define LINK_STATUS BIT(1)
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#define DUPLEX_STATUS BIT(2)
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#define SPEED_STATUS_SHIFT 3
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#define SPEED_STATUS_10 0
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#define SPEED_STATUS_100 1
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#define SPEED_STATUS_1000 2
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#define SPEED_STATUS_2500 3
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#define SPEED_STATUS_MASK SPEED_STATUS_2500
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#define PAUSE_RESOLUTION_TX_SIDE BIT(5)
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#define PAUSE_RESOLUTION_RX_SIDE BIT(6)
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#define LINK_STATUS_CHANGE BIT(7)
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#define EARLY_END_EXT_DET BIT(8)
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#define CARRIER_EXT_ERR_DET BIT(9)
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#define RX_ERR_DET BIT(10)
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#define TX_ERR_DET BIT(11)
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#define CRC_ERR_DET BIT(12)
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#define FALSE_CARRIER_ERR_DET BIT(13)
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#define RXFIFO_ERR_DET BIT(14)
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#define TXFIFO_ERR_DET BIT(15)
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/* Block offsets */
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#define SERDES_DIGITAL_BLK 0x8300
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#define SERDES_ID0 0x8310
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#define SERDES_MII_BLK 0xffe0
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#define SERDES_XGXSBLK0_BLOCKADDRESS 0xffd0
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struct phylink_link_state;
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static inline u8 b53_serdes_map_lane(struct b53_device *dev, int port)
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{
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if (!dev->ops->serdes_map_lane)
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return B53_INVALID_LANE;
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return dev->ops->serdes_map_lane(dev, port);
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}
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int b53_serdes_get_link(struct b53_device *dev, int port);
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int b53_serdes_link_state(struct b53_device *dev, int port,
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struct phylink_link_state *state);
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void b53_serdes_config(struct b53_device *dev, int port, unsigned int mode,
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const struct phylink_link_state *state);
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void b53_serdes_an_restart(struct b53_device *dev, int port);
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void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
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phy_interface_t interface, bool link_up);
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void b53_serdes_phylink_validate(struct b53_device *dev, int port,
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unsigned long *supported,
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struct phylink_link_state *state);
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#if IS_ENABLED(CONFIG_B53_SERDES)
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int b53_serdes_init(struct b53_device *dev, int port);
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#else
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static inline int b53_serdes_init(struct b53_device *dev, int port)
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{
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return -ENODEV;
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}
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#endif
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