/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
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* Author:Mark Yao <mark.yao@rock-chips.com>
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*/
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#ifndef _ROCKCHIP_DRM_VOP_H
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#define _ROCKCHIP_DRM_VOP_H
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#include <drm/drm_plane.h>
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#include <drm/drm_modes.h>
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#include "rockchip_drm_drv.h"
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/*
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* major: IP major version, used for IP structure
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* minor: big feature change under same structure
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* build: RTL current SVN number
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*/
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#define VOP_VERSION(major, minor) ((major) << 8 | (minor))
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#define VOP_MAJOR(version) ((version) >> 8)
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#define VOP_MINOR(version) ((version) & 0xff)
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#define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build))
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#define VOP2_MAJOR(version) (((version) >> 24) & 0xff)
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#define VOP2_MINOR(version) (((version) >> 16) & 0xff)
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#define VOP2_BUILD(version) ((version) & 0xffff)
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#define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
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#define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350)
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#define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
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#define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
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#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
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#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
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#define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
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/* MIPI DSI DataStream(cmd) mode on rk3588 */
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#define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3)
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#define AFBDC_FMT_RGB565 0x0
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#define AFBDC_FMT_U8U8U8U8 0x5
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#define AFBDC_FMT_U8U8U8 0x4
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#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
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#define VOP_FEATURE_INTERNAL_RGB BIT(1)
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#define VOP_FEATURE_ALPHA_SCALE BIT(2)
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#define VOP_FEATURE_HDR10 BIT(3)
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#define VOP_FEATURE_NEXT_HDR BIT(4)
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/* a feature to splice two windows and two vps to support resolution > 4096 */
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#define VOP_FEATURE_SPLICE BIT(5)
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#define VOP_FEATURE_OVERSCAN BIT(6)
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#define VOP_FEATURE_VIVID_HDR BIT(7)
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#define VOP_FEATURE_POST_ACM BIT(8)
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#define VOP_FEATURE_POST_CSC BIT(9)
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#define VOP_FEATURE_OUTPUT_10BIT VOP_FEATURE_OUTPUT_RGB10
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#define WIN_FEATURE_HDR2SDR BIT(0)
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#define WIN_FEATURE_SDR2HDR BIT(1)
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#define WIN_FEATURE_PRE_OVERLAY BIT(2)
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#define WIN_FEATURE_AFBDC BIT(3)
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#define WIN_FEATURE_CLUSTER_MAIN BIT(4)
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#define WIN_FEATURE_CLUSTER_SUB BIT(5)
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/* Left win in splice mode */
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#define WIN_FEATURE_SPLICE_LEFT BIT(6)
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/* a mirror win can only get fb address
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* from source win:
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* Cluster1---->Cluster0
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* Esmart1 ---->Esmart0
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* Smart1 ---->Smart0
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* This is a feather on rk3566
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*/
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#define WIN_FEATURE_MIRROR BIT(6)
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#define WIN_FEATURE_MULTI_AREA BIT(7)
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#define WIN_FEATURE_Y2R_13BIT_DEPTH BIT(8)
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#define VOP2_SOC_VARIANT 4
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#define ROCKCHIP_DSC_PPS_SIZE_BYTE 88
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enum vop_vp_id {
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ROCKCHIP_VOP_VP0 = 0,
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ROCKCHIP_VOP_VP1,
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ROCKCHIP_VOP_VP2,
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ROCKCHIP_VOP_VP3,
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};
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enum vop_win_phy_id {
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ROCKCHIP_VOP_WIN0 = 0,
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ROCKCHIP_VOP_WIN1,
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ROCKCHIP_VOP_WIN2,
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ROCKCHIP_VOP_WIN3,
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ROCKCHIP_VOP_PHY_ID_INVALID = -1,
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};
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enum bcsh_out_mode {
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BCSH_OUT_MODE_BLACK,
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BCSH_OUT_MODE_BLUE,
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BCSH_OUT_MODE_COLOR_BAR,
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BCSH_OUT_MODE_NORMAL_VIDEO,
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};
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enum cabc_stage_mode {
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LAST_FRAME_PWM_VAL = 0x0,
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CUR_FRAME_PWM_VAL = 0x1,
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STAGE_BY_STAGE = 0x2
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};
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enum cabc_stage_up_mode {
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MUL_MODE,
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ADD_MODE,
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};
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/*
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* the delay number of a window in different mode.
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*/
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enum vop2_win_dly_mode {
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VOP2_DLY_MODE_DEFAULT, /**< default mode */
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VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */
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VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */
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VOP2_DLY_MODE_MAX,
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};
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enum vop3_esmart_lb_mode {
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VOP3_ESMART_8K_MODE,
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VOP3_ESMART_4K_4K_MODE,
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VOP3_ESMART_4K_2K_2K_MODE,
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VOP3_ESMART_2K_2K_2K_2K_MODE,
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};
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/*
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* vop2 dsc id
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*/
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#define ROCKCHIP_VOP2_DSC_8K 0
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#define ROCKCHIP_VOP2_DSC_4K 1
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/*
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* vop2 internal power domain id,
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* should be all none zero, 0 will be
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* treat as invalid;
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*/
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#define VOP2_PD_CLUSTER0 BIT(0)
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#define VOP2_PD_CLUSTER1 BIT(1)
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#define VOP2_PD_CLUSTER2 BIT(2)
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#define VOP2_PD_CLUSTER3 BIT(3)
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#define VOP2_PD_DSC_8K BIT(5)
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#define VOP2_PD_DSC_4K BIT(6)
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#define VOP2_PD_ESMART BIT(7)
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/*
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* vop2 submem power gate,
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* should be all none zero, 0 will be
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* treat as invalid;
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*/
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#define VOP2_MEM_PG_VP0 BIT(0)
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#define VOP2_MEM_PG_VP1 BIT(1)
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#define VOP2_MEM_PG_VP2 BIT(2)
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#define VOP2_MEM_PG_VP3 BIT(3)
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#define VOP2_MEM_PG_DB0 BIT(4)
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#define VOP2_MEM_PG_DB1 BIT(5)
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#define VOP2_MEM_PG_DB2 BIT(6)
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#define VOP2_MEM_PG_WB BIT(7)
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#define DSP_BG_SWAP 0x1
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#define DSP_RB_SWAP 0x2
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#define DSP_RG_SWAP 0x4
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#define DSP_DELTA_SWAP 0x8
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#define V4L2_COLORSPACE_BT709F 0xfe
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#define V4L2_COLORSPACE_BT2020F 0xff
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enum vop_csc_format {
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CSC_BT601L,
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CSC_BT709L,
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CSC_BT601F,
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CSC_BT2020,
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CSC_BT709L_13BIT,
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CSC_BT709F_13BIT,
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CSC_BT2020L_13BIT,
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CSC_BT2020F_13BIT,
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};
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enum vop_csc_mode {
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CSC_RGB,
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CSC_YUV,
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};
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enum vop_csc_bit_depth {
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CSC_10BIT_DEPTH,
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CSC_13BIT_DEPTH,
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};
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enum vop_data_format {
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VOP_FMT_ARGB8888 = 0,
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VOP_FMT_RGB888,
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VOP_FMT_RGB565 = 2,
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VOP_FMT_YUYV = 2,
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VOP_FMT_YUV420SP = 4,
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VOP_FMT_YUV422SP,
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VOP_FMT_YUV444SP,
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};
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enum vop_dsc_interface_mode {
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VOP_DSC_IF_DISABLE = 0,
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VOP_DSC_IF_HDMI = 1,
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VOP_DSC_IF_MIPI_DS_MODE = 2,
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VOP_DSC_IF_MIPI_VIDEO_MODE = 3,
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};
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struct vop_reg_data {
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uint32_t offset;
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uint32_t value;
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};
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struct vop_reg {
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uint32_t mask;
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uint32_t offset:17;
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uint32_t shift:5;
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uint32_t begin_minor:4;
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uint32_t end_minor:4;
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uint32_t reserved:2;
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uint32_t major:3;
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uint32_t write_mask:1;
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};
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struct vop_csc {
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struct vop_reg y2r_en;
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struct vop_reg r2r_en;
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struct vop_reg r2y_en;
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struct vop_reg csc_mode;
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uint32_t y2r_offset;
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uint32_t r2r_offset;
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uint32_t r2y_offset;
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};
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struct vop_rect {
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int width;
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int height;
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};
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struct vop_ctrl {
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struct vop_reg version;
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struct vop_reg standby;
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struct vop_reg dma_stop;
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struct vop_reg axi_outstanding_max_num;
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struct vop_reg axi_max_outstanding_en;
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struct vop_reg htotal_pw;
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struct vop_reg hact_st_end;
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struct vop_reg vtotal_pw;
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struct vop_reg vact_st_end;
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struct vop_reg vact_st_end_f1;
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struct vop_reg vs_st_end_f1;
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struct vop_reg hpost_st_end;
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struct vop_reg vpost_st_end;
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struct vop_reg vpost_st_end_f1;
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struct vop_reg post_scl_factor;
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struct vop_reg post_scl_ctrl;
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struct vop_reg dsp_interlace;
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struct vop_reg dsp_interlace_pol;
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struct vop_reg global_regdone_en;
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struct vop_reg auto_gate_en;
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struct vop_reg post_lb_mode;
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struct vop_reg dsp_layer_sel;
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struct vop_reg overlay_mode;
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struct vop_reg core_dclk_div;
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struct vop_reg dclk_ddr;
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struct vop_reg p2i_en;
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struct vop_reg hdmi_dclk_out_en;
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struct vop_reg rgb_en;
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struct vop_reg lvds_en;
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struct vop_reg edp_en;
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struct vop_reg hdmi_en;
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struct vop_reg mipi_en;
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struct vop_reg data01_swap;
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struct vop_reg mipi_dual_channel_en;
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struct vop_reg dp_en;
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struct vop_reg dclk_pol;
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struct vop_reg pin_pol;
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struct vop_reg rgb_dclk_pol;
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struct vop_reg rgb_pin_pol;
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struct vop_reg lvds_dclk_pol;
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struct vop_reg lvds_pin_pol;
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struct vop_reg hdmi_dclk_pol;
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struct vop_reg hdmi_pin_pol;
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struct vop_reg edp_dclk_pol;
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struct vop_reg edp_pin_pol;
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struct vop_reg mipi_dclk_pol;
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struct vop_reg mipi_pin_pol;
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struct vop_reg dp_dclk_pol;
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struct vop_reg dp_pin_pol;
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struct vop_reg dither_down_sel;
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struct vop_reg dither_down_mode;
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struct vop_reg dither_down_en;
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struct vop_reg pre_dither_down_en;
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struct vop_reg dither_up_en;
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struct vop_reg sw_dac_sel;
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struct vop_reg tve_sw_mode;
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struct vop_reg tve_dclk_pol;
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struct vop_reg tve_dclk_en;
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struct vop_reg sw_genlock;
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struct vop_reg sw_uv_offset_en;
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struct vop_reg dsp_out_yuv;
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struct vop_reg dsp_data_swap;
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struct vop_reg dsp_bg_swap;
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struct vop_reg dsp_rb_swap;
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struct vop_reg dsp_rg_swap;
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struct vop_reg dsp_delta_swap;
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struct vop_reg dsp_dummy_swap;
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struct vop_reg yuv_clip;
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struct vop_reg dsp_ccir656_avg;
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struct vop_reg dsp_black;
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struct vop_reg dsp_blank;
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struct vop_reg dsp_outzero;
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struct vop_reg update_gamma_lut;
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struct vop_reg lut_buffer_index;
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struct vop_reg dsp_lut_en;
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struct vop_reg out_mode;
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struct vop_reg xmirror;
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struct vop_reg ymirror;
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struct vop_reg dsp_background;
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/* AFBDC */
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struct vop_reg afbdc_en;
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struct vop_reg afbdc_sel;
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struct vop_reg afbdc_format;
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struct vop_reg afbdc_hreg_block_split;
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struct vop_reg afbdc_pic_size;
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struct vop_reg afbdc_hdr_ptr;
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struct vop_reg afbdc_rstn;
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struct vop_reg afbdc_pic_vir_width;
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struct vop_reg afbdc_pic_offset;
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struct vop_reg afbdc_axi_ctrl;
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/* BCSH */
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struct vop_reg bcsh_brightness;
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struct vop_reg bcsh_contrast;
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struct vop_reg bcsh_sat_con;
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struct vop_reg bcsh_sin_hue;
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struct vop_reg bcsh_cos_hue;
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struct vop_reg bcsh_r2y_csc_mode;
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struct vop_reg bcsh_r2y_en;
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struct vop_reg bcsh_y2r_csc_mode;
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struct vop_reg bcsh_y2r_en;
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struct vop_reg bcsh_color_bar;
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struct vop_reg bcsh_out_mode;
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struct vop_reg bcsh_en;
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/* HDR */
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struct vop_reg level2_overlay_en;
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struct vop_reg alpha_hard_calc;
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struct vop_reg hdr2sdr_en;
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struct vop_reg hdr2sdr_en_win0_csc;
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struct vop_reg hdr2sdr_src_min;
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struct vop_reg hdr2sdr_src_max;
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struct vop_reg hdr2sdr_normfaceetf;
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struct vop_reg hdr2sdr_dst_min;
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struct vop_reg hdr2sdr_dst_max;
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struct vop_reg hdr2sdr_normfacgamma;
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struct vop_reg bt1886eotf_pre_conv_en;
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struct vop_reg rgb2rgb_pre_conv_en;
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struct vop_reg rgb2rgb_pre_conv_mode;
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struct vop_reg st2084oetf_pre_conv_en;
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struct vop_reg bt1886eotf_post_conv_en;
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struct vop_reg rgb2rgb_post_conv_en;
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struct vop_reg rgb2rgb_post_conv_mode;
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struct vop_reg st2084oetf_post_conv_en;
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struct vop_reg win_csc_mode_sel;
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/* MCU OUTPUT */
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struct vop_reg mcu_pix_total;
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struct vop_reg mcu_cs_pst;
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struct vop_reg mcu_cs_pend;
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struct vop_reg mcu_rw_pst;
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struct vop_reg mcu_rw_pend;
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struct vop_reg mcu_clk_sel;
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struct vop_reg mcu_hold_mode;
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struct vop_reg mcu_frame_st;
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struct vop_reg mcu_rs;
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struct vop_reg mcu_bypass;
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struct vop_reg mcu_type;
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struct vop_reg mcu_rw_bypass_port;
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/* bt1120 */
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struct vop_reg bt1120_yc_swap;
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struct vop_reg bt1120_en;
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/* bt656 */
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struct vop_reg bt656_en;
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struct vop_reg reg_done_frm;
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struct vop_reg cfg_done;
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};
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struct vop_intr {
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const int *intrs;
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uint32_t nintrs;
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struct vop_reg line_flag_num[2];
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struct vop_reg enable;
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struct vop_reg clear;
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struct vop_reg status;
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};
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struct vop_scl_extension {
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struct vop_reg cbcr_vsd_mode;
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struct vop_reg cbcr_vsu_mode;
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struct vop_reg cbcr_hsd_mode;
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struct vop_reg cbcr_ver_scl_mode;
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struct vop_reg cbcr_hor_scl_mode;
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struct vop_reg yrgb_vsd_mode;
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struct vop_reg yrgb_vsu_mode;
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struct vop_reg yrgb_hsd_mode;
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struct vop_reg yrgb_ver_scl_mode;
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struct vop_reg yrgb_hor_scl_mode;
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struct vop_reg line_load_mode;
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struct vop_reg cbcr_axi_gather_num;
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struct vop_reg yrgb_axi_gather_num;
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struct vop_reg vsd_cbcr_gt2;
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struct vop_reg vsd_cbcr_gt4;
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struct vop_reg vsd_yrgb_gt2;
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struct vop_reg vsd_yrgb_gt4;
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struct vop_reg bic_coe_sel;
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struct vop_reg cbcr_axi_gather_en;
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struct vop_reg yrgb_axi_gather_en;
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struct vop_reg lb_mode;
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};
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struct vop_scl_regs {
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const struct vop_scl_extension *ext;
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struct vop_reg scale_yrgb_x;
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struct vop_reg scale_yrgb_y;
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struct vop_reg scale_cbcr_x;
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struct vop_reg scale_cbcr_y;
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};
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struct vop_afbc {
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struct vop_reg enable;
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struct vop_reg win_sel;
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struct vop_reg format;
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struct vop_reg rb_swap;
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struct vop_reg uv_swap;
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struct vop_reg auto_gating_en;
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struct vop_reg rotate;
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struct vop_reg block_split_en;
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struct vop_reg pic_vir_width;
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struct vop_reg tile_num;
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struct vop_reg pic_offset;
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struct vop_reg pic_size;
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struct vop_reg dsp_offset;
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struct vop_reg transform_offset;
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struct vop_reg hdr_ptr;
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struct vop_reg half_block_en;
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struct vop_reg xmirror;
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struct vop_reg ymirror;
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struct vop_reg rotate_270;
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struct vop_reg rotate_90;
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struct vop_reg rstn;
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};
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struct vop_csc_table {
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const uint32_t *y2r_bt601;
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const uint32_t *y2r_bt601_12_235;
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const uint32_t *y2r_bt601_10bit;
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const uint32_t *y2r_bt601_10bit_12_235;
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const uint32_t *r2y_bt601;
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const uint32_t *r2y_bt601_12_235;
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const uint32_t *r2y_bt601_10bit;
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const uint32_t *r2y_bt601_10bit_12_235;
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const uint32_t *y2r_bt709;
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const uint32_t *y2r_bt709_10bit;
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const uint32_t *r2y_bt709;
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const uint32_t *r2y_bt709_10bit;
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const uint32_t *y2r_bt2020;
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const uint32_t *r2y_bt2020;
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const uint32_t *r2r_bt709_to_bt2020;
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const uint32_t *r2r_bt2020_to_bt709;
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};
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struct vop_hdr_table {
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const uint32_t hdr2sdr_eetf_oetf_y0_offset;
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const uint32_t hdr2sdr_eetf_oetf_y1_offset;
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const uint32_t *hdr2sdr_eetf_yn;
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const uint32_t *hdr2sdr_bt1886oetf_yn;
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const uint32_t hdr2sdr_sat_y0_offset;
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const uint32_t hdr2sdr_sat_y1_offset;
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const uint32_t *hdr2sdr_sat_yn;
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const uint32_t hdr2sdr_src_range_min;
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const uint32_t hdr2sdr_src_range_max;
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const uint32_t hdr2sdr_normfaceetf;
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const uint32_t hdr2sdr_dst_range_min;
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const uint32_t hdr2sdr_dst_range_max;
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const uint32_t hdr2sdr_normfacgamma;
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const uint32_t sdr2hdr_eotf_oetf_y0_offset;
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const uint32_t sdr2hdr_eotf_oetf_y1_offset;
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const uint32_t *sdr2hdr_bt1886eotf_yn_for_hlg_hdr;
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const uint32_t *sdr2hdr_bt1886eotf_yn_for_bt2020;
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const uint32_t *sdr2hdr_bt1886eotf_yn_for_hdr;
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const uint32_t *sdr2hdr_st2084oetf_yn_for_hlg_hdr;
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const uint32_t *sdr2hdr_st2084oetf_yn_for_bt2020;
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const uint32_t *sdr2hdr_st2084oetf_yn_for_hdr;
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const uint32_t sdr2hdr_oetf_dx_dxpow1_offset;
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const uint32_t *sdr2hdr_st2084oetf_dxn_pow2;
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const uint32_t *sdr2hdr_st2084oetf_dxn;
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const uint32_t sdr2hdr_oetf_xn1_offset;
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const uint32_t *sdr2hdr_st2084oetf_xn;
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};
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#define RK_HDRVIVID_TONE_SCA_TAB_LENGTH 257
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#define RK_HDRVIVID_GAMMA_CURVE_LENGTH 81
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#define RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH 9
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#define RK_SDR2HDR_INVGAMMA_CURVE_LENGTH 69
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#define RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH 6
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#define RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH 6
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#define RK_SDR2HDR_SMGAIN_LENGTH 64
|
#define RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH 264
|
|
struct hdrvivid_regs {
|
uint32_t sdr2hdr_ctrl;
|
uint32_t sdr2hdr_coe0;
|
uint32_t sdr2hdr_coe1;
|
uint32_t sdr2hdr_csc_coe00_01;
|
uint32_t sdr2hdr_csc_coe02_10;
|
uint32_t sdr2hdr_csc_coe11_12;
|
uint32_t sdr2hdr_csc_coe20_21;
|
uint32_t sdr2hdr_csc_coe22;
|
uint32_t hdrvivid_ctrl;
|
uint32_t hdr_pq_gamma;
|
uint32_t hlg_rfix_scalefac;
|
uint32_t hlg_maxluma;
|
uint32_t hlg_r_tm_lin2non;
|
uint32_t hdr_csc_coe00_01;
|
uint32_t hdr_csc_coe02_10;
|
uint32_t hdr_csc_coe11_12;
|
uint32_t hdr_csc_coe20_21;
|
uint32_t hdr_csc_coe22;
|
uint32_t hdr_tone_sca[RK_HDRVIVID_TONE_SCA_TAB_LENGTH];
|
uint32_t hdrgamma_curve[RK_HDRVIVID_GAMMA_CURVE_LENGTH];
|
uint32_t hdrgamma_mdfvalue[RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH];
|
uint32_t sdrinvgamma_curve[RK_SDR2HDR_INVGAMMA_CURVE_LENGTH];
|
uint32_t sdrinvgamma_startidx[RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH];
|
uint32_t sdrinvgamma_changeidx[RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH];
|
uint32_t sdr_smgain[RK_SDR2HDR_SMGAIN_LENGTH];
|
uint32_t hdr_mode;
|
uint32_t tone_sca_axi_tab[RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH];
|
};
|
|
struct hdr_extend {
|
uint32_t hdr_type;
|
uint32_t length;
|
union {
|
struct hdrvivid_regs hdrvivid_data;
|
};
|
};
|
|
enum _vop_hdrvivid_mode {
|
PQHDR2HDR_WITH_DYNAMIC = 0,
|
PQHDR2SDR_WITH_DYNAMIC,
|
HLG2PQHDR_WITH_DYNAMIC,
|
HLG2SDR_WITH_DYNAMIC,
|
HLG2PQHDR_WITHOUT_DYNAMIC,
|
HLG2SDR_WITHOUT_DYNAMIC,
|
HDR_BYPASS,
|
HDR102SDR,
|
SDR2HDR10,
|
SDR2HLG,
|
SDR2HDR10_USERSPACE = 100,
|
SDR2HLG_USERSPACE = 101,
|
};
|
|
enum vop_hdr_format {
|
HDR_NONE = 0,
|
HDR_HDR10 = 1,
|
HDR_HLGSTATIC = 2,
|
RESERVED3 = 3, /* reserved for more future static hdr format */
|
RESERVED4 = 4, /* reserved for more future static hdr format */
|
HDR_HDRVIVID = 5,
|
RESERVED6 = 6, /* reserved for hdr vivid */
|
RESERVED7 = 7, /* reserved for hdr vivid */
|
HDR_HDR10PLUS = 8,
|
RESERVED9 = 9, /* reserved for hdr hdr10+ */
|
RESERVED10 = 10, /* reserved for hdr hdr10+ */
|
HDR_NEXT = 11,
|
RESERVED12 = 12, /* reserved for other dynamic hdr format */
|
RESERVED13 = 13, /* reserved for other dynamic hdr format */
|
HDR_FORMAT_MAX,
|
};
|
|
#define ACM_GAIN_LUT_HY_LENGTH (9*17)
|
#define ACM_GAIN_LUT_HY_TOTAL_LENGTH (ACM_GAIN_LUT_HY_LENGTH * 3)
|
#define ACM_GAIN_LUT_HS_LENGTH (13*17)
|
#define ACM_GAIN_LUT_HS_TOTAL_LENGTH (ACM_GAIN_LUT_HS_LENGTH * 3)
|
#define ACM_DELTA_LUT_H_LENGTH 65
|
#define ACM_DELTA_LUT_H_TOTAL_LENGTH (ACM_DELTA_LUT_H_LENGTH * 3)
|
|
struct post_acm {
|
s16 delta_lut_h[ACM_DELTA_LUT_H_TOTAL_LENGTH];
|
s16 gain_lut_hy[ACM_GAIN_LUT_HY_TOTAL_LENGTH];
|
s16 gain_lut_hs[ACM_GAIN_LUT_HS_TOTAL_LENGTH];
|
u16 y_gain;
|
u16 h_gain;
|
u16 s_gain;
|
u16 acm_enable;
|
};
|
|
struct post_csc {
|
u16 hue;
|
u16 saturation;
|
u16 contrast;
|
u16 brightness;
|
u16 r_gain;
|
u16 g_gain;
|
u16 b_gain;
|
u16 r_offset;
|
u16 g_offset;
|
u16 b_offset;
|
u16 csc_enable;
|
};
|
|
struct post_csc_coef {
|
s32 csc_coef00;
|
s32 csc_coef01;
|
s32 csc_coef02;
|
s32 csc_coef10;
|
s32 csc_coef11;
|
s32 csc_coef12;
|
s32 csc_coef20;
|
s32 csc_coef21;
|
s32 csc_coef22;
|
|
s32 csc_dc0;
|
s32 csc_dc1;
|
s32 csc_dc2;
|
|
u32 range_type;
|
};
|
|
enum {
|
VOP_CSC_Y2R_BT601,
|
VOP_CSC_Y2R_BT709,
|
VOP_CSC_Y2R_BT2020,
|
VOP_CSC_R2Y_BT601,
|
VOP_CSC_R2Y_BT709,
|
VOP_CSC_R2Y_BT2020,
|
VOP_CSC_R2R_BT2020_TO_BT709,
|
VOP_CSC_R2R_BT709_TO_2020,
|
};
|
|
enum _vop_overlay_mode {
|
VOP_RGB_DOMAIN,
|
VOP_YUV_DOMAIN
|
};
|
|
enum _vop_sdr2hdr_func {
|
SDR2HDR_FOR_BT2020,
|
SDR2HDR_FOR_HDR,
|
SDR2HDR_FOR_HLG_HDR,
|
};
|
|
enum _vop_rgb2rgb_conv_mode {
|
BT709_TO_BT2020,
|
BT2020_TO_BT709,
|
};
|
|
enum _MCU_IOCTL {
|
MCU_WRCMD = 0,
|
MCU_WRDATA,
|
MCU_SETBYPASS,
|
};
|
|
struct vop_win_phy {
|
const struct vop_scl_regs *scl;
|
const uint32_t *data_formats;
|
uint32_t nformats;
|
|
struct vop_reg gate;
|
struct vop_reg enable;
|
struct vop_reg format;
|
struct vop_reg interlace_read;
|
struct vop_reg fmt_10;
|
struct vop_reg fmt_yuyv;
|
struct vop_reg csc_mode;
|
struct vop_reg xmirror;
|
struct vop_reg ymirror;
|
struct vop_reg rb_swap;
|
struct vop_reg act_info;
|
struct vop_reg dsp_info;
|
struct vop_reg dsp_st;
|
struct vop_reg yrgb_mst;
|
struct vop_reg uv_mst;
|
struct vop_reg yrgb_vir;
|
struct vop_reg uv_vir;
|
|
struct vop_reg channel;
|
struct vop_reg dst_alpha_ctl;
|
struct vop_reg src_alpha_ctl;
|
struct vop_reg alpha_mode;
|
struct vop_reg alpha_en;
|
struct vop_reg alpha_pre_mul;
|
struct vop_reg global_alpha_val;
|
struct vop_reg color_key;
|
struct vop_reg color_key_en;
|
};
|
|
struct vop_win_data {
|
uint32_t base;
|
enum drm_plane_type type;
|
const struct vop_win_phy *phy;
|
const struct vop_win_phy **area;
|
const uint64_t *format_modifiers;
|
const struct vop_csc *csc;
|
unsigned int area_size;
|
u64 feature;
|
};
|
|
struct vop2_cluster_regs {
|
struct vop_reg enable;
|
struct vop_reg afbc_enable;
|
struct vop_reg lb_mode;
|
struct vop_reg scl_lb_mode;
|
struct vop_reg frm_reset_en;
|
|
struct vop_reg src_color_ctrl;
|
struct vop_reg dst_color_ctrl;
|
struct vop_reg src_alpha_ctrl;
|
struct vop_reg dst_alpha_ctrl;
|
};
|
|
struct vop2_scl_regs {
|
struct vop_reg scale_yrgb_x;
|
struct vop_reg scale_yrgb_y;
|
struct vop_reg scale_cbcr_x;
|
struct vop_reg scale_cbcr_y;
|
struct vop_reg yrgb_hor_scl_mode;
|
struct vop_reg yrgb_hscl_filter_mode;
|
struct vop_reg yrgb_ver_scl_mode;
|
struct vop_reg yrgb_vscl_filter_mode;
|
struct vop_reg cbcr_ver_scl_mode;
|
struct vop_reg cbcr_hscl_filter_mode;
|
struct vop_reg cbcr_hor_scl_mode;
|
struct vop_reg cbcr_vscl_filter_mode;
|
struct vop_reg vsd_cbcr_gt2;
|
struct vop_reg vsd_cbcr_gt4;
|
struct vop_reg vsd_yrgb_gt2;
|
struct vop_reg vsd_yrgb_gt4;
|
struct vop_reg bic_coe_sel;
|
struct vop_reg xavg_en; /* supported from vop3 */
|
struct vop_reg xgt_en;
|
struct vop_reg xgt_mode;
|
struct vop_reg vsd_avg2;
|
struct vop_reg vsd_avg4;
|
};
|
|
struct vop2_win_regs {
|
const struct vop2_scl_regs *scl;
|
const struct vop2_cluster_regs *cluster;
|
const struct vop_afbc *afbc;
|
|
struct vop_reg gate;
|
struct vop_reg enable;
|
struct vop_reg format;
|
struct vop_reg tile_mode;
|
struct vop_reg csc_mode;
|
struct vop_reg csc_13bit_en;
|
struct vop_reg xmirror;
|
struct vop_reg ymirror;
|
struct vop_reg rb_swap;
|
struct vop_reg uv_swap;
|
struct vop_reg act_info;
|
struct vop_reg dsp_info;
|
struct vop_reg dsp_st;
|
struct vop_reg yrgb_mst;
|
struct vop_reg uv_mst;
|
struct vop_reg yrgb_vir;
|
struct vop_reg uv_vir;
|
struct vop_reg yuv_clip;
|
struct vop_reg lb_mode;
|
struct vop_reg y2r_en;
|
struct vop_reg r2y_en;
|
struct vop_reg channel;
|
struct vop_reg dst_alpha_ctl;
|
struct vop_reg src_alpha_ctl;
|
struct vop_reg alpha_mode;
|
struct vop_reg alpha_en;
|
struct vop_reg global_alpha_val;
|
struct vop_reg color_key;
|
struct vop_reg color_key_en;
|
struct vop_reg dither_up;
|
struct vop_reg axi_id;
|
struct vop_reg axi_yrgb_id;
|
struct vop_reg axi_uv_id;
|
struct vop_reg scale_engine_num;
|
};
|
|
struct vop2_video_port_regs {
|
struct vop_reg cfg_done;
|
struct vop_reg overlay_mode;
|
struct vop_reg dsp_background;
|
struct vop_reg port_mux;
|
struct vop_reg out_mode;
|
struct vop_reg standby;
|
struct vop_reg dsp_interlace;
|
struct vop_reg dsp_filed_pol;
|
struct vop_reg dsp_data_swap;
|
struct vop_reg dsp_x_mir_en;
|
struct vop_reg post_dsp_out_r2y;
|
struct vop_reg pre_scan_htiming;
|
struct vop_reg htotal_pw;
|
struct vop_reg hact_st_end;
|
struct vop_reg dsp_vtotal;
|
struct vop_reg sw_dsp_vtotal_imd;
|
struct vop_reg dsp_vs_end;
|
struct vop_reg vact_st_end;
|
struct vop_reg vact_st_end_f1;
|
struct vop_reg vs_st_end_f1;
|
struct vop_reg hpost_st_end;
|
struct vop_reg vpost_st_end;
|
struct vop_reg vpost_st_end_f1;
|
struct vop_reg post_scl_factor;
|
struct vop_reg post_scl_ctrl;
|
struct vop_reg dither_down_sel;
|
struct vop_reg dither_down_mode;
|
struct vop_reg dither_down_en;
|
struct vop_reg pre_dither_down_en;
|
struct vop_reg dither_up_en;
|
struct vop_reg bg_dly;
|
|
struct vop_reg core_dclk_div;
|
struct vop_reg p2i_en;
|
struct vop_reg dual_channel_en;
|
struct vop_reg dual_channel_swap;
|
struct vop_reg dsp_lut_en;
|
|
struct vop_reg dclk_div2;
|
struct vop_reg dclk_div2_phase_lock;
|
|
struct vop_reg hdr10_en;
|
struct vop_reg hdr_lut_update_en;
|
struct vop_reg hdr_lut_mode;
|
struct vop_reg hdr_lut_mst;
|
struct vop_reg hdr_lut_fetch_done;
|
struct vop_reg hdr_vivid_en;
|
struct vop_reg hdr_vivid_bypass_en;
|
struct vop_reg hdr_vivid_path_mode;
|
struct vop_reg hdr_vivid_dstgamut;
|
struct vop_reg sdr2hdr_en;
|
struct vop_reg sdr2hdr_dstmode;
|
struct vop_reg sdr2hdr_eotf_en;
|
struct vop_reg sdr2hdr_r2r_en;
|
struct vop_reg sdr2hdr_r2r_mode;
|
struct vop_reg sdr2hdr_oetf_en;
|
struct vop_reg sdr2hdr_bypass_en;
|
struct vop_reg sdr2hdr_auto_gating_en;
|
struct vop_reg sdr2hdr_path_en;
|
struct vop_reg hdr2sdr_en;
|
struct vop_reg hdr2sdr_bypass_en;
|
struct vop_reg hdr2sdr_auto_gating_en;
|
struct vop_reg hdr2sdr_src_min;
|
struct vop_reg hdr2sdr_src_max;
|
struct vop_reg hdr2sdr_normfaceetf;
|
struct vop_reg hdr2sdr_dst_min;
|
struct vop_reg hdr2sdr_dst_max;
|
struct vop_reg hdr2sdr_normfacgamma;
|
uint32_t hdr2sdr_eetf_oetf_y0_offset;
|
uint32_t hdr2sdr_sat_y0_offset;
|
uint32_t sdr2hdr_eotf_oetf_y0_offset;
|
uint32_t sdr2hdr_oetf_dx_pow1_offset;
|
uint32_t sdr2hdr_oetf_xn1_offset;
|
struct vop_reg hdr_src_color_ctrl;
|
struct vop_reg hdr_dst_color_ctrl;
|
struct vop_reg hdr_src_alpha_ctrl;
|
struct vop_reg hdr_dst_alpha_ctrl;
|
struct vop_reg bg_mix_ctrl;
|
struct vop_reg layer_sel;
|
|
/* BCSH */
|
struct vop_reg bcsh_brightness;
|
struct vop_reg bcsh_contrast;
|
struct vop_reg bcsh_sat_con;
|
struct vop_reg bcsh_sin_hue;
|
struct vop_reg bcsh_cos_hue;
|
struct vop_reg bcsh_r2y_csc_mode;
|
struct vop_reg bcsh_r2y_en;
|
struct vop_reg bcsh_y2r_csc_mode;
|
struct vop_reg bcsh_y2r_en;
|
struct vop_reg bcsh_out_mode;
|
struct vop_reg bcsh_en;
|
|
/* 3d lut */
|
struct vop_reg cubic_lut_en;
|
struct vop_reg cubic_lut_update_en;
|
struct vop_reg cubic_lut_mst;
|
|
/* cru */
|
struct vop_reg dclk_core_div;
|
struct vop_reg dclk_out_div;
|
struct vop_reg dclk_src_sel;
|
|
struct vop_reg splice_en;
|
|
struct vop_reg edpi_wms_hold_en;
|
struct vop_reg edpi_te_en;
|
struct vop_reg edpi_wms_fs;
|
struct vop_reg gamma_update_en;
|
struct vop_reg lut_dma_rid;
|
|
/* MCU output */
|
struct vop_reg mcu_pix_total;
|
struct vop_reg mcu_cs_pst;
|
struct vop_reg mcu_cs_pend;
|
struct vop_reg mcu_rw_pst;
|
struct vop_reg mcu_rw_pend;
|
struct vop_reg mcu_clk_sel;
|
struct vop_reg mcu_hold_mode;
|
struct vop_reg mcu_frame_st;
|
struct vop_reg mcu_rs;
|
struct vop_reg mcu_bypass;
|
struct vop_reg mcu_type;
|
struct vop_reg mcu_rw_bypass_port;
|
|
/* for DCF */
|
struct vop_reg line_flag_or_en;
|
struct vop_reg dsp_hold_or_en;
|
struct vop_reg almost_full_or_en;
|
|
/* CSC */
|
struct vop_reg acm_bypass_en;
|
struct vop_reg csc_en;
|
struct vop_reg acm_r2y_en;
|
struct vop_reg csc_mode;
|
struct vop_reg acm_r2y_mode;
|
struct vop_reg csc_coe00;
|
struct vop_reg csc_coe01;
|
struct vop_reg csc_coe02;
|
struct vop_reg csc_coe10;
|
struct vop_reg csc_coe11;
|
struct vop_reg csc_coe12;
|
struct vop_reg csc_coe20;
|
struct vop_reg csc_coe21;
|
struct vop_reg csc_coe22;
|
struct vop_reg csc_offset0;
|
struct vop_reg csc_offset1;
|
struct vop_reg csc_offset2;
|
|
/* color bar */
|
struct vop_reg color_bar_en;
|
struct vop_reg color_bar_mode;
|
};
|
|
struct vop2_power_domain_regs {
|
struct vop_reg pd;
|
struct vop_reg status;
|
struct vop_reg bisr_en_status;
|
struct vop_reg pmu_status;
|
};
|
|
struct vop2_dsc_regs {
|
/* DSC SYS CTRL */
|
struct vop_reg dsc_port_sel;
|
struct vop_reg dsc_man_mode;
|
struct vop_reg dsc_interface_mode;
|
struct vop_reg dsc_pixel_num;
|
struct vop_reg dsc_pxl_clk_div;
|
struct vop_reg dsc_cds_clk_div;
|
struct vop_reg dsc_txp_clk_div;
|
struct vop_reg dsc_init_dly_mode;
|
struct vop_reg dsc_scan_en;
|
struct vop_reg dsc_halt_en;
|
struct vop_reg rst_deassert;
|
struct vop_reg dsc_flush;
|
struct vop_reg dsc_cfg_done;
|
struct vop_reg dsc_init_dly_num;
|
struct vop_reg scan_timing_para_imd_en;
|
struct vop_reg dsc_htotal_pw;
|
struct vop_reg dsc_hact_st_end;
|
struct vop_reg dsc_vtotal;
|
struct vop_reg dsc_vs_end;
|
struct vop_reg dsc_vact_st_end;
|
struct vop_reg dsc_error_status;
|
|
/* DSC encoder */
|
struct vop_reg dsc_pps0_3;
|
struct vop_reg dsc_en;
|
struct vop_reg dsc_rbit;
|
struct vop_reg dsc_rbyt;
|
struct vop_reg dsc_flal;
|
struct vop_reg dsc_mer;
|
struct vop_reg dsc_epb;
|
struct vop_reg dsc_epl;
|
struct vop_reg dsc_nslc;
|
struct vop_reg dsc_sbo;
|
struct vop_reg dsc_ifep;
|
struct vop_reg dsc_pps_upd;
|
struct vop_reg dsc_status;
|
struct vop_reg dsc_ecw;
|
};
|
|
struct vop2_wb_regs {
|
struct vop_reg enable;
|
struct vop_reg format;
|
struct vop_reg dither_en;
|
struct vop_reg r2y_en;
|
struct vop_reg yrgb_mst;
|
struct vop_reg uv_mst;
|
struct vop_reg vp_id;
|
struct vop_reg fifo_throd;
|
struct vop_reg scale_x_factor;
|
struct vop_reg scale_x_en;
|
struct vop_reg scale_y_en;
|
struct vop_reg axi_yrgb_id;
|
struct vop_reg axi_uv_id;
|
};
|
|
struct vop2_power_domain_data {
|
uint8_t id;
|
uint8_t parent_id;
|
/*
|
* @module_id_mask: module id of which module this power domain is belongs to.
|
* PD_CLUSTER0,1,2,3 only belongs to CLUSTER0/1/2/3, PD_Esmart0 shared by Esmart1/2/3
|
*/
|
uint32_t module_id_mask;
|
|
const struct vop2_power_domain_regs *regs;
|
};
|
|
/*
|
* connector interface(RGB/HDMI/eDP/DP/MIPI) data
|
*/
|
struct vop2_connector_if_data {
|
u32 id;
|
const char *clk_src_name;
|
const char *clk_parent_name;
|
const char *pixclk_name;
|
const char *dclk_name;
|
u32 post_proc_div_shift;
|
u32 if_div_shift;
|
u32 if_div_yuv420_shift;
|
u32 bus_div_shift;
|
u32 pixel_clk_div_shift;
|
};
|
|
struct vop2_win_data {
|
const char *name;
|
uint8_t phys_id;
|
uint8_t splice_win_id;
|
uint8_t pd_id;
|
uint8_t axi_id;
|
uint8_t axi_yrgb_id;
|
uint8_t axi_uv_id;
|
uint8_t possible_crtcs;
|
|
uint32_t base;
|
enum drm_plane_type type;
|
|
uint32_t nformats;
|
const uint32_t *formats;
|
const uint64_t *format_modifiers;
|
const unsigned int supported_rotations;
|
|
const struct vop2_win_regs *regs;
|
const struct vop2_win_regs **area;
|
unsigned int area_size;
|
|
/*
|
* vertical/horizontal scale up/down filter mode
|
*/
|
const u8 hsu_filter_mode;
|
const u8 hsd_filter_mode;
|
const u8 vsu_filter_mode;
|
const u8 vsd_filter_mode;
|
const u8 hsd_pre_filter_mode;
|
const u8 vsd_pre_filter_mode;
|
/**
|
* @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2
|
*/
|
const uint8_t layer_sel_id[ROCKCHIP_MAX_CRTC];
|
uint64_t feature;
|
|
unsigned int max_upscale_factor;
|
unsigned int max_downscale_factor;
|
const uint8_t dly[VOP2_DLY_MODE_MAX];
|
};
|
|
struct dsc_error_info {
|
u32 dsc_error_val;
|
char dsc_error_info[50];
|
};
|
|
struct vop2_dsc_data {
|
uint8_t id;
|
uint8_t pd_id;
|
uint8_t max_slice_num;
|
uint8_t max_linebuf_depth; /* used to generate the bitstream */
|
uint8_t min_bits_per_pixel; /* bit num after encoder compress */
|
const char *dsc_txp_clk_src_name;
|
const char *dsc_txp_clk_name;
|
const char *dsc_pxl_clk_name;
|
const char *dsc_cds_clk_name;
|
const struct vop2_dsc_regs *regs;
|
};
|
|
struct vop2_wb_data {
|
uint32_t nformats;
|
const uint32_t *formats;
|
struct vop_rect max_output;
|
const struct vop2_wb_regs *regs;
|
uint32_t fifo_depth;
|
};
|
|
struct vop3_ovl_mix_regs {
|
struct vop_reg src_color_ctrl;
|
struct vop_reg dst_color_ctrl;
|
struct vop_reg src_alpha_ctrl;
|
struct vop_reg dst_alpha_ctrl;
|
};
|
|
struct vop3_ovl_regs {
|
const struct vop3_ovl_mix_regs *layer_mix_regs;
|
const struct vop3_ovl_mix_regs *hdr_mix_regs;
|
};
|
|
struct vop2_video_port_data {
|
char id;
|
uint8_t splice_vp_id;
|
uint16_t lut_dma_rid;
|
uint32_t feature;
|
uint64_t soc_id[VOP2_SOC_VARIANT];
|
uint16_t gamma_lut_len;
|
uint16_t cubic_lut_len;
|
unsigned long dclk_max;
|
struct vop_rect max_output;
|
const u8 pre_scan_max_dly[4];
|
const u8 hdrvivid_dly[10];
|
const u8 sdr2hdr_dly;
|
const u8 layer_mix_dly;
|
const u8 hdr_mix_dly;
|
const u8 win_dly;
|
const struct vop_intr *intr;
|
const struct vop_hdr_table *hdr_table;
|
const struct vop2_video_port_regs *regs;
|
const struct vop3_ovl_regs *ovl_regs;
|
};
|
|
struct vop2_layer_regs {
|
struct vop_reg layer_sel;
|
};
|
|
/**
|
* struct vop2_layer_data - The logic graphic layer in vop2
|
*
|
* The zorder:
|
* LAYERn
|
* LAYERn-1
|
* .
|
* .
|
* .
|
* LAYER5
|
* LAYER4
|
* LAYER3
|
* LAYER2
|
* LAYER1
|
* LAYER0
|
*
|
* Each layer can select a unused window as input than feed to
|
* mixer for overlay.
|
*
|
* The pipeline in vop2:
|
*
|
* win-->layer-->mixer-->vp--->connector(RGB/LVDS/HDMI/MIPI)
|
*
|
*/
|
struct vop2_layer_data {
|
char id;
|
const struct vop2_layer_regs *regs;
|
};
|
|
struct vop_grf_ctrl {
|
struct vop_reg grf_dclk_inv;
|
struct vop_reg grf_bt1120_clk_inv;
|
struct vop_reg grf_bt656_clk_inv;
|
struct vop_reg grf_edp0_en;
|
struct vop_reg grf_edp1_en;
|
struct vop_reg grf_hdmi0_en;
|
struct vop_reg grf_hdmi1_en;
|
struct vop_reg grf_hdmi0_dsc_en;
|
struct vop_reg grf_hdmi1_dsc_en;
|
struct vop_reg grf_hdmi0_pin_pol;
|
struct vop_reg grf_hdmi1_pin_pol;
|
};
|
|
struct vop_data {
|
const struct vop_reg_data *init_table;
|
unsigned int table_size;
|
const struct vop_ctrl *ctrl;
|
const struct vop_intr *intr;
|
const struct vop_win_data *win;
|
const struct vop_csc_table *csc_table;
|
const struct vop_hdr_table *hdr_table;
|
const struct vop_grf_ctrl *grf_ctrl;
|
unsigned int win_size;
|
uint32_t version;
|
struct vop_rect max_input;
|
struct vop_rect max_output;
|
u64 feature;
|
u64 soc_id;
|
u8 vop_id;
|
};
|
|
struct vop2_ctrl {
|
struct vop_reg cfg_done_en;
|
struct vop_reg wb_cfg_done;
|
struct vop_reg auto_gating_en;
|
struct vop_reg aclk_pre_auto_gating_en;
|
struct vop_reg dma_finish_mode;
|
struct vop_reg axi_dma_finish_and_en;
|
struct vop_reg wb_dma_finish_and_en;
|
struct vop_reg ovl_cfg_done_port;
|
struct vop_reg ovl_port_mux_cfg_done_imd;
|
struct vop_reg ovl_port_mux_cfg;
|
struct vop_reg if_ctrl_cfg_done_imd;
|
struct vop_reg version;
|
struct vop_reg standby;
|
struct vop_reg dma_stop;
|
struct vop_reg dsp_vs_t_sel;
|
struct vop_reg lut_dma_en;
|
struct vop_reg axi_outstanding_max_num;
|
struct vop_reg axi_max_outstanding_en;
|
struct vop_reg hdmi_dclk_out_en;
|
struct vop_reg rgb_en;
|
struct vop_reg hdmi0_en;
|
struct vop_reg hdmi1_en;
|
struct vop_reg dp0_en;
|
struct vop_reg dp1_en;
|
struct vop_reg edp0_en;
|
struct vop_reg edp1_en;
|
struct vop_reg mipi0_en;
|
struct vop_reg mipi1_en;
|
struct vop_reg lvds0_en;
|
struct vop_reg lvds1_en;
|
struct vop_reg bt656_en;
|
struct vop_reg bt1120_en;
|
struct vop_reg bt656_dclk_pol;
|
struct vop_reg bt1120_dclk_pol;
|
struct vop_reg dclk_pol;
|
struct vop_reg pin_pol;
|
struct vop_reg rgb_dclk_pol;
|
struct vop_reg rgb_pin_pol;
|
struct vop_reg lvds_dclk_pol;
|
struct vop_reg lvds_pin_pol;
|
struct vop_reg hdmi_dclk_pol;
|
struct vop_reg hdmi_pin_pol;
|
struct vop_reg edp_dclk_pol;
|
struct vop_reg edp_pin_pol;
|
struct vop_reg mipi_dclk_pol;
|
struct vop_reg mipi_pin_pol;
|
struct vop_reg dp0_dclk_pol;
|
struct vop_reg dp0_pin_pol;
|
struct vop_reg dp1_dclk_pol;
|
struct vop_reg dp1_pin_pol;
|
|
/* This will be reference by win_phy_id */
|
struct vop_reg win_vp_id[16];
|
struct vop_reg win_dly[16];
|
|
/* connector mux */
|
struct vop_reg rgb_mux;
|
struct vop_reg hdmi0_mux;
|
struct vop_reg hdmi1_mux;
|
struct vop_reg dp0_mux;
|
struct vop_reg dp1_mux;
|
struct vop_reg edp0_mux;
|
struct vop_reg edp1_mux;
|
struct vop_reg mipi0_mux;
|
struct vop_reg mipi1_mux;
|
struct vop_reg lvds0_mux;
|
struct vop_reg lvds1_mux;
|
|
struct vop_reg lvds_dual_en;
|
struct vop_reg lvds_dual_mode;
|
struct vop_reg lvds_dual_channel_swap;
|
|
struct vop_reg dp_dual_en;
|
struct vop_reg edp_dual_en;
|
struct vop_reg hdmi_dual_en;
|
struct vop_reg mipi_dual_en;
|
|
struct vop_reg hdmi0_dclk_div;
|
struct vop_reg hdmi0_pixclk_div;
|
struct vop_reg edp0_dclk_div;
|
struct vop_reg edp0_pixclk_div;
|
|
struct vop_reg hdmi1_dclk_div;
|
struct vop_reg hdmi1_pixclk_div;
|
struct vop_reg edp1_dclk_div;
|
struct vop_reg edp1_pixclk_div;
|
|
struct vop_reg mipi0_pixclk_div;
|
struct vop_reg mipi1_pixclk_div;
|
struct vop_reg mipi0_ds_mode;
|
struct vop_reg mipi1_ds_mode;
|
|
struct vop_reg src_color_ctrl;
|
struct vop_reg dst_color_ctrl;
|
struct vop_reg src_alpha_ctrl;
|
struct vop_reg dst_alpha_ctrl;
|
|
struct vop_reg bt1120_yc_swap;
|
struct vop_reg bt656_yc_swap;
|
struct vop_reg gamma_port_sel;
|
struct vop_reg pd_off_imd;
|
|
struct vop_reg otp_en;
|
struct vop_reg esmart_lb_mode;
|
struct vop_reg reg_done_frm;
|
struct vop_reg cfg_done;
|
};
|
|
struct vop_dump_regs {
|
uint32_t offset;
|
const char *name;
|
struct vop_reg state;
|
bool enable_state;
|
};
|
|
struct vop2_vp_plane_mask {
|
u8 primary_plane_id;
|
u8 attached_layers_nr;
|
u8 attached_layers[ROCKCHIP_MAX_LAYER];
|
};
|
|
/**
|
* VOP2 data structe
|
*
|
* @version: VOP IP version
|
* @win_size: hardware win number
|
*/
|
struct vop2_data {
|
uint32_t version;
|
uint32_t feature;
|
uint8_t nr_dscs;
|
uint8_t nr_dsc_ecw;
|
uint8_t nr_dsc_buffer_flow;
|
uint8_t nr_vps;
|
uint8_t nr_mixers;
|
uint8_t nr_layers;
|
uint8_t nr_axi_intr;
|
uint8_t nr_gammas;
|
uint8_t nr_conns;
|
uint8_t nr_pds;
|
uint8_t nr_mem_pgs;
|
uint8_t esmart_lb_mode;
|
bool delayed_pd;
|
const struct vop_intr *axi_intr;
|
const struct vop2_ctrl *ctrl;
|
const struct vop2_dsc_data *dsc;
|
const struct dsc_error_info *dsc_error_ecw;
|
const struct dsc_error_info *dsc_error_buffer_flow;
|
const struct vop2_win_data *win;
|
const struct vop2_video_port_data *vp;
|
const struct vop2_connector_if_data *conn;
|
const struct vop2_wb_data *wb;
|
const struct vop2_layer_data *layer;
|
const struct vop2_power_domain_data *pd;
|
const struct vop2_power_domain_data *mem_pg;
|
const struct vop_csc_table *csc_table;
|
const struct vop_hdr_table *hdr_table;
|
const struct vop_grf_ctrl *sys_grf;
|
const struct vop_grf_ctrl *grf;
|
const struct vop_grf_ctrl *vo0_grf;
|
const struct vop_grf_ctrl *vo1_grf;
|
const struct vop_dump_regs *dump_regs;
|
uint32_t dump_regs_size;
|
struct vop_rect max_input;
|
struct vop_rect max_output;
|
const struct vop2_vp_plane_mask *plane_mask;
|
uint32_t plane_mask_base;
|
|
unsigned int win_size;
|
};
|
|
#define CVBS_PAL_VDISPLAY 288
|
|
/* interrupt define */
|
#define DSP_HOLD_VALID_INTR BIT(0)
|
#define FS_INTR BIT(1)
|
#define LINE_FLAG_INTR BIT(2)
|
#define BUS_ERROR_INTR BIT(3)
|
#define FS_NEW_INTR BIT(4)
|
#define ADDR_SAME_INTR BIT(5)
|
#define LINE_FLAG1_INTR BIT(6)
|
#define WIN0_EMPTY_INTR BIT(7)
|
#define WIN1_EMPTY_INTR BIT(8)
|
#define WIN2_EMPTY_INTR BIT(9)
|
#define WIN3_EMPTY_INTR BIT(10)
|
#define HWC_EMPTY_INTR BIT(11)
|
#define POST_BUF_EMPTY_INTR BIT(12)
|
#define PWM_GEN_INTR BIT(13)
|
#define DMA_FINISH_INTR BIT(14)
|
#define FS_FIELD_INTR BIT(15)
|
#define FE_INTR BIT(16)
|
#define WB_UV_FIFO_FULL_INTR BIT(17)
|
#define WB_YRGB_FIFO_FULL_INTR BIT(18)
|
#define WB_COMPLETE_INTR BIT(19)
|
|
#define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
|
LINE_FLAG_INTR | BUS_ERROR_INTR | \
|
FS_NEW_INTR | LINE_FLAG1_INTR | \
|
WIN0_EMPTY_INTR | WIN1_EMPTY_INTR | \
|
WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | \
|
HWC_EMPTY_INTR | \
|
POST_BUF_EMPTY_INTR | \
|
DMA_FINISH_INTR | FS_FIELD_INTR | \
|
FE_INTR)
|
#define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
|
#define FS_INTR_EN(x) ((x) << 5)
|
#define LINE_FLAG_INTR_EN(x) ((x) << 6)
|
#define BUS_ERROR_INTR_EN(x) ((x) << 7)
|
#define DSP_HOLD_VALID_INTR_MASK (1 << 4)
|
#define FS_INTR_MASK (1 << 5)
|
#define LINE_FLAG_INTR_MASK (1 << 6)
|
#define BUS_ERROR_INTR_MASK (1 << 7)
|
|
#define INTR_CLR_SHIFT 8
|
#define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
|
#define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
|
#define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
|
#define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
|
|
#define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
|
#define DSP_LINE_NUM_MASK (0x1fff << 12)
|
|
/* src alpha ctrl define */
|
#define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
|
#define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
|
#define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
|
#define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
|
#define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
|
#define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
|
#define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
|
#define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
|
/* dst alpha ctrl define */
|
#define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
|
|
/*
|
* display output interface supported by rockchip lcdc
|
*/
|
#define ROCKCHIP_OUT_MODE_P888 0
|
#define ROCKCHIP_OUT_MODE_BT1120 0
|
#define ROCKCHIP_OUT_MODE_P666 1
|
#define ROCKCHIP_OUT_MODE_P565 2
|
#define ROCKCHIP_OUT_MODE_BT656 5
|
#define ROCKCHIP_OUT_MODE_S888 8
|
#define ROCKCHIP_OUT_MODE_YUV422 9
|
#define ROCKCHIP_OUT_MODE_S888_DUMMY 12
|
#define ROCKCHIP_OUT_MODE_YUV420 14
|
/* for use special outface */
|
#define ROCKCHIP_OUT_MODE_AAAA 15
|
|
#define ROCKCHIP_OUT_MODE_TYPE(x) ((x) >> 16)
|
#define ROCKCHIP_OUT_MODE(x) ((x) & 0xffff)
|
|
enum alpha_mode {
|
ALPHA_STRAIGHT,
|
ALPHA_INVERSE,
|
};
|
|
enum global_blend_mode {
|
ALPHA_GLOBAL,
|
ALPHA_PER_PIX,
|
ALPHA_PER_PIX_GLOBAL,
|
};
|
|
enum alpha_cal_mode {
|
ALPHA_SATURATION,
|
ALPHA_NO_SATURATION,
|
};
|
|
enum color_mode {
|
ALPHA_SRC_PRE_MUL,
|
ALPHA_SRC_NO_PRE_MUL,
|
};
|
|
enum factor_mode {
|
ALPHA_ZERO,
|
ALPHA_ONE,
|
ALPHA_SRC,
|
ALPHA_SRC_INVERSE,
|
ALPHA_SRC_GLOBAL,
|
ALPHA_DST_GLOBAL,
|
};
|
|
enum src_factor_mode {
|
SRC_FAC_ALPHA_ZERO,
|
SRC_FAC_ALPHA_ONE,
|
SRC_FAC_ALPHA_DST,
|
SRC_FAC_ALPHA_DST_INVERSE,
|
SRC_FAC_ALPHA_SRC,
|
SRC_FAC_ALPHA_SRC_GLOBAL,
|
};
|
|
enum dst_factor_mode {
|
DST_FAC_ALPHA_ZERO,
|
DST_FAC_ALPHA_ONE,
|
DST_FAC_ALPHA_SRC,
|
DST_FAC_ALPHA_SRC_INVERSE,
|
DST_FAC_ALPHA_DST,
|
DST_FAC_ALPHA_DST_GLOBAL,
|
};
|
|
enum scale_mode {
|
SCALE_NONE = 0x0,
|
SCALE_UP = 0x1,
|
SCALE_DOWN = 0x2
|
};
|
|
enum lb_mode {
|
LB_YUV_3840X5 = 0x0,
|
LB_YUV_2560X8 = 0x1,
|
LB_RGB_3840X2 = 0x2,
|
LB_RGB_2560X4 = 0x3,
|
LB_RGB_1920X5 = 0x4,
|
LB_RGB_1280X8 = 0x5
|
};
|
|
enum sacle_up_mode {
|
SCALE_UP_BIL = 0x0,
|
SCALE_UP_BIC = 0x1
|
};
|
|
enum scale_down_mode {
|
SCALE_DOWN_BIL = 0x0,
|
SCALE_DOWN_AVG = 0x1
|
};
|
|
enum vop2_scale_up_mode {
|
VOP2_SCALE_UP_NRST_NBOR,
|
VOP2_SCALE_UP_BIL,
|
VOP2_SCALE_UP_BIC,
|
};
|
|
enum vop2_scale_down_mode {
|
VOP2_SCALE_DOWN_NRST_NBOR,
|
VOP2_SCALE_DOWN_BIL,
|
VOP2_SCALE_DOWN_AVG,
|
};
|
|
enum vop3_pre_scale_down_mode {
|
VOP3_PRE_SCALE_UNSPPORT,
|
VOP3_PRE_SCALE_DOWN_GT,
|
VOP3_PRE_SCALE_DOWN_AVG,
|
};
|
|
enum dither_down_mode {
|
RGB888_TO_RGB565 = 0x0,
|
RGB888_TO_RGB666 = 0x1
|
};
|
|
enum dither_down_mode_sel {
|
DITHER_DOWN_ALLEGRO = 0x0,
|
DITHER_DOWN_FRC = 0x1
|
};
|
|
enum vop_pol {
|
HSYNC_POSITIVE = 0,
|
VSYNC_POSITIVE = 1,
|
DEN_NEGATIVE = 2,
|
DCLK_INVERT = 3
|
};
|
|
|
#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
|
#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
|
#define SCL_MAX_VSKIPLINES 4
|
#define MIN_SCL_FT_AFTER_VSKIP 1
|
|
static inline uint16_t scl_cal_scale(int src, int dst, int shift)
|
{
|
return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
|
}
|
|
static inline uint16_t scl_cal_scale2(int src, int dst)
|
{
|
return ((src - 1) << 12) / (dst - 1);
|
}
|
|
#define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
|
#define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
|
#define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
|
|
static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
|
int vskiplines)
|
{
|
int act_height;
|
|
act_height = (src_h + vskiplines - 1) / vskiplines;
|
|
if (act_height == dst_h)
|
return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
|
|
return GET_SCL_FT_BILI_DN(act_height, dst_h);
|
}
|
|
static inline enum scale_mode scl_get_scl_mode(int src, int dst)
|
{
|
if (src < dst)
|
return SCALE_UP;
|
else if (src > dst)
|
return SCALE_DOWN;
|
|
return SCALE_NONE;
|
}
|
|
static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
|
{
|
uint32_t vskiplines;
|
|
for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
|
if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
|
break;
|
|
return vskiplines;
|
}
|
|
static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
|
{
|
int lb_mode;
|
|
if (is_yuv) {
|
if (width > 1280)
|
lb_mode = LB_YUV_3840X5;
|
else
|
lb_mode = LB_YUV_2560X8;
|
} else {
|
if (width > 2560)
|
lb_mode = LB_RGB_3840X2;
|
else if (width > 1920)
|
lb_mode = LB_RGB_2560X4;
|
else
|
lb_mode = LB_RGB_1920X5;
|
}
|
|
return lb_mode;
|
}
|
|
static inline int us_to_vertical_line(struct drm_display_mode *mode, int us)
|
{
|
return us * mode->clock / mode->htotal / 1000;
|
}
|
|
static inline int interpolate(int x1, int y1, int x2, int y2, int x)
|
{
|
return y1 + (y2 - y1) * (x - x1) / (x2 - x1);
|
}
|
|
extern const struct component_ops vop_component_ops;
|
extern const struct component_ops vop2_component_ops;
|
#endif /* _ROCKCHIP_DRM_VOP_H */
|
