/*
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _clk_10_0_2_SH_MASK_HEADER
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#define _clk_10_0_2_SH_MASK_HEADER
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// addressBlock: clk_clk1_0_SmuClkDec
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//CLK1_CLK_PLL_REQ
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#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
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#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
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#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
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#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
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#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
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#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
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//CLK1_CLK0_BYPASS_CNTL
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#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT 0x0
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#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT 0x10
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#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK 0x00000007L
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#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK 0x000F0000L
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//CLK1_CLK1_BYPASS_CNTL
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#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT 0x0
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#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT 0x10
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#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK 0x00000007L
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#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK 0x000F0000L
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//CLK1_CLK2_BYPASS_CNTL
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#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0
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#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10
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#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
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#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L
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//CLK1_CLK3_DS_CNTL
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#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT 0x0
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#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK 0x00000007L
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//CLK1_CLK3_ALLOW_DS
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#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT 0x0
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#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK 0x00000001L
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//CLK1_CLK3_BYPASS_CNTL
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#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT 0x0
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#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT 0x10
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#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK 0x00000007L
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#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK 0x000F0000L
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//CLK1_CLK0_CURRENT_CNT
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#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0
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#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL
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//CLK1_CLK1_CURRENT_CNT
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#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0
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#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL
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//CLK1_CLK2_CURRENT_CNT
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#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0
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#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL
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//CLK1_CLK3_CURRENT_CNT
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#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0
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#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL
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#endif
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