/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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/*
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* Pre-requisites: headers required by header of this unit
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*/
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#include "include/gpio_types.h"
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/*
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* Header of this unit
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*/
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#include "hw_translate.h"
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/*
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* Post-requisites: headers required by this unit
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*/
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#if defined(CONFIG_DRM_AMD_DC_SI)
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#include "dce60/hw_translate_dce60.h"
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#endif
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#include "dce80/hw_translate_dce80.h"
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#include "dce110/hw_translate_dce110.h"
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#include "dce120/hw_translate_dce120.h"
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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#include "dcn10/hw_translate_dcn10.h"
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#include "dcn20/hw_translate_dcn20.h"
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#include "dcn21/hw_translate_dcn21.h"
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#endif
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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#include "dcn30/hw_translate_dcn30.h"
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#endif
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#include "diagnostics/hw_translate_diag.h"
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/*
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* This unit
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*/
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bool dal_hw_translate_init(
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struct hw_translate *translate,
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enum dce_version dce_version,
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enum dce_environment dce_environment)
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{
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if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
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dal_hw_translate_diag_fpga_init(translate);
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return true;
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}
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switch (dce_version) {
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#if defined(CONFIG_DRM_AMD_DC_SI)
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case DCE_VERSION_6_0:
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case DCE_VERSION_6_1:
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case DCE_VERSION_6_4:
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dal_hw_translate_dce60_init(translate);
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return true;
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#endif
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case DCE_VERSION_8_0:
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case DCE_VERSION_8_1:
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case DCE_VERSION_8_3:
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dal_hw_translate_dce80_init(translate);
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return true;
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case DCE_VERSION_10_0:
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case DCE_VERSION_11_0:
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case DCE_VERSION_11_2:
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case DCE_VERSION_11_22:
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dal_hw_translate_dce110_init(translate);
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return true;
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case DCE_VERSION_12_0:
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case DCE_VERSION_12_1:
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dal_hw_translate_dce120_init(translate);
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return true;
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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case DCN_VERSION_1_0:
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case DCN_VERSION_1_01:
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dal_hw_translate_dcn10_init(translate);
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return true;
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case DCN_VERSION_2_0:
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dal_hw_translate_dcn20_init(translate);
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return true;
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case DCN_VERSION_2_1:
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dal_hw_translate_dcn21_init(translate);
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return true;
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#endif
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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case DCN_VERSION_3_0:
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dal_hw_translate_dcn30_init(translate);
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return true;
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#endif
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default:
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BREAK_TO_DEBUGGER();
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return false;
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}
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}
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