/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "reg_helper.h"
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#include <linux/delay.h>
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#include "core_types.h"
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#include "link_encoder.h"
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#include "dcn21_link_encoder.h"
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#include "stream_encoder.h"
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#include "i2caux_interface.h"
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#include "dc_bios_types.h"
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#include "gpio_service_interface.h"
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#define CTX \
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enc10->base.ctx
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#define DC_LOGGER \
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enc10->base.ctx->logger
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#define REG(reg)\
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(enc10->link_regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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enc10->link_shift->field_name, enc10->link_mask->field_name
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#define IND_REG(index) \
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(enc10->link_regs->index)
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static struct mpll_cfg dcn21_mpll_cfg_ref[] = {
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// RBR
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{
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.hdmimode_enable = 0,
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.ref_range = 1,
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.ref_clk_mpllb_div = 1,
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.mpllb_ssc_en = 1,
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.mpllb_div5_clk_en = 1,
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.mpllb_multiplier = 238,
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.mpllb_fracn_en = 0,
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.mpllb_fracn_quot = 0,
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.mpllb_fracn_rem = 0,
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.mpllb_fracn_den = 1,
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.mpllb_ssc_up_spread = 0,
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.mpllb_ssc_peak = 44237,
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.mpllb_ssc_stepsize = 59454,
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.mpllb_div_clk_en = 0,
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.mpllb_div_multiplier = 0,
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.mpllb_hdmi_div = 0,
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.mpllb_tx_clk_div = 2,
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.tx_vboost_lvl = 5,
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.mpllb_pmix_en = 1,
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.mpllb_word_div2_en = 0,
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.mpllb_ana_v2i = 2,
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.mpllb_ana_freq_vco = 2,
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.mpllb_ana_cp_int = 9,
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.mpllb_ana_cp_prop = 15,
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.hdmi_pixel_clk_div = 0,
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},
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// HBR
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{
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.hdmimode_enable = 0,
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.ref_range = 1,
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.ref_clk_mpllb_div = 1,
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.mpllb_ssc_en = 1,
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.mpllb_div5_clk_en = 1,
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.mpllb_multiplier = 192,
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.mpllb_fracn_en = 1,
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.mpllb_fracn_quot = 32768,
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.mpllb_fracn_rem = 0,
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.mpllb_fracn_den = 1,
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.mpllb_ssc_up_spread = 0,
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.mpllb_ssc_peak = 36864,
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.mpllb_ssc_stepsize = 49545,
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.mpllb_div_clk_en = 0,
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.mpllb_div_multiplier = 0,
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.mpllb_hdmi_div = 0,
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.mpllb_tx_clk_div = 1,
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.tx_vboost_lvl = 5,
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.mpllb_pmix_en = 1,
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.mpllb_word_div2_en = 0,
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.mpllb_ana_v2i = 2,
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.mpllb_ana_freq_vco = 3,
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.mpllb_ana_cp_int = 9,
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.mpllb_ana_cp_prop = 15,
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.hdmi_pixel_clk_div = 0,
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},
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//HBR2
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{
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.hdmimode_enable = 0,
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.ref_range = 1,
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.ref_clk_mpllb_div = 1,
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.mpllb_ssc_en = 1,
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.mpllb_div5_clk_en = 1,
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.mpllb_multiplier = 192,
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.mpllb_fracn_en = 1,
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.mpllb_fracn_quot = 32768,
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.mpllb_fracn_rem = 0,
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.mpllb_fracn_den = 1,
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.mpllb_ssc_up_spread = 0,
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.mpllb_ssc_peak = 36864,
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.mpllb_ssc_stepsize = 49545,
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.mpllb_div_clk_en = 0,
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.mpllb_div_multiplier = 0,
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.mpllb_hdmi_div = 0,
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.mpllb_tx_clk_div = 0,
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.tx_vboost_lvl = 5,
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.mpllb_pmix_en = 1,
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.mpllb_word_div2_en = 0,
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.mpllb_ana_v2i = 2,
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.mpllb_ana_freq_vco = 3,
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.mpllb_ana_cp_int = 9,
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.mpllb_ana_cp_prop = 15,
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.hdmi_pixel_clk_div = 0,
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},
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//HBR3
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{
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.hdmimode_enable = 0,
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.ref_range = 1,
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.ref_clk_mpllb_div = 1,
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.mpllb_ssc_en = 1,
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.mpllb_div5_clk_en = 1,
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.mpllb_multiplier = 304,
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.mpllb_fracn_en = 1,
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.mpllb_fracn_quot = 49152,
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.mpllb_fracn_rem = 0,
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.mpllb_fracn_den = 1,
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.mpllb_ssc_up_spread = 0,
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.mpllb_ssc_peak = 55296,
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.mpllb_ssc_stepsize = 74318,
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.mpllb_div_clk_en = 0,
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.mpllb_div_multiplier = 0,
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.mpllb_hdmi_div = 0,
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.mpllb_tx_clk_div = 0,
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.tx_vboost_lvl = 5,
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.mpllb_pmix_en = 1,
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.mpllb_word_div2_en = 0,
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.mpllb_ana_v2i = 2,
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.mpllb_ana_freq_vco = 1,
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.mpllb_ana_cp_int = 7,
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.mpllb_ana_cp_prop = 16,
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.hdmi_pixel_clk_div = 0,
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},
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};
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static bool update_cfg_data(
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struct dcn10_link_encoder *enc10,
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const struct dc_link_settings *link_settings,
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struct dpcssys_phy_seq_cfg *cfg)
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{
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int i;
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cfg->load_sram_fw = false;
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cfg->use_calibration_setting = true;
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//TODO: need to implement a proper lane mapping for Renoir.
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for (i = 0; i < 4; i++)
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cfg->lane_en[i] = true;
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switch (link_settings->link_rate) {
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case LINK_RATE_LOW:
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cfg->mpll_cfg = dcn21_mpll_cfg_ref[0];
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break;
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case LINK_RATE_HIGH:
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cfg->mpll_cfg = dcn21_mpll_cfg_ref[1];
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break;
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case LINK_RATE_HIGH2:
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cfg->mpll_cfg = dcn21_mpll_cfg_ref[2];
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break;
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case LINK_RATE_HIGH3:
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cfg->mpll_cfg = dcn21_mpll_cfg_ref[3];
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break;
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default:
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DC_LOG_ERROR("%s: No supported link rate found %X!\n",
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__func__, link_settings->link_rate);
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return false;
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}
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return true;
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}
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bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc)
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{
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struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
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int value;
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if (enc->features.flags.bits.DP_IS_USB_C) {
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REG_GET(RDPCSTX_PHY_CNTL6,
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RDPCS_PHY_DPALT_DISABLE, &value);
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if (value == 1) {
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ASSERT(0);
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return false;
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}
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REG_UPDATE(RDPCSTX_PHY_CNTL6,
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RDPCS_PHY_DPALT_DISABLE_ACK, 0);
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udelay(40);
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REG_GET(RDPCSTX_PHY_CNTL6,
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RDPCS_PHY_DPALT_DISABLE, &value);
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if (value == 1) {
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ASSERT(0);
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REG_UPDATE(RDPCSTX_PHY_CNTL6,
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RDPCS_PHY_DPALT_DISABLE_ACK, 1);
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return false;
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}
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}
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REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 1);
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return true;
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}
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static void dcn21_link_encoder_release_phy(struct link_encoder *enc)
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{
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struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
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if (enc->features.flags.bits.DP_IS_USB_C) {
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REG_UPDATE(RDPCSTX_PHY_CNTL6,
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RDPCS_PHY_DPALT_DISABLE_ACK, 1);
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}
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REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 0);
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}
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void dcn21_link_encoder_enable_dp_output(
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struct link_encoder *enc,
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const struct dc_link_settings *link_settings,
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enum clock_source_id clock_source)
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{
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struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
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struct dcn21_link_encoder *enc21 = (struct dcn21_link_encoder *) enc10;
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struct dpcssys_phy_seq_cfg *cfg = &enc21->phy_seq_cfg;
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if (!dcn21_link_encoder_acquire_phy(enc))
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return;
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if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
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dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
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return;
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}
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if (!update_cfg_data(enc10, link_settings, cfg))
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return;
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enc1_configure_encoder(enc10, link_settings);
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dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT);
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}
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void dcn21_link_encoder_enable_dp_mst_output(
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struct link_encoder *enc,
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const struct dc_link_settings *link_settings,
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enum clock_source_id clock_source)
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{
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if (!dcn21_link_encoder_acquire_phy(enc))
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return;
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dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
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}
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void dcn21_link_encoder_disable_output(
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struct link_encoder *enc,
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enum signal_type signal)
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{
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dcn10_link_encoder_disable_output(enc, signal);
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if (dc_is_dp_signal(signal))
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dcn21_link_encoder_release_phy(enc);
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}
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static const struct link_encoder_funcs dcn21_link_enc_funcs = {
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.read_state = link_enc2_read_state,
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.validate_output_with_stream =
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dcn10_link_encoder_validate_output_with_stream,
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.hw_init = enc2_hw_init,
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.setup = dcn10_link_encoder_setup,
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.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
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.enable_dp_output = dcn21_link_encoder_enable_dp_output,
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.enable_dp_mst_output = dcn21_link_encoder_enable_dp_mst_output,
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.disable_output = dcn21_link_encoder_disable_output,
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.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
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.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
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.update_mst_stream_allocation_table =
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dcn10_link_encoder_update_mst_stream_allocation_table,
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.psr_program_dp_dphy_fast_training =
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dcn10_psr_program_dp_dphy_fast_training,
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.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
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.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
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.enable_hpd = dcn10_link_encoder_enable_hpd,
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.disable_hpd = dcn10_link_encoder_disable_hpd,
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.is_dig_enabled = dcn10_is_dig_enabled,
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.destroy = dcn10_link_encoder_destroy,
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.fec_set_enable = enc2_fec_set_enable,
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.fec_set_ready = enc2_fec_set_ready,
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.fec_is_active = enc2_fec_is_active,
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.get_dig_frontend = dcn10_get_dig_frontend,
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.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
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.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
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};
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void dcn21_link_encoder_construct(
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struct dcn21_link_encoder *enc21,
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const struct encoder_init_data *init_data,
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const struct encoder_feature_support *enc_features,
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const struct dcn10_link_enc_registers *link_regs,
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const struct dcn10_link_enc_aux_registers *aux_regs,
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const struct dcn10_link_enc_hpd_registers *hpd_regs,
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const struct dcn10_link_enc_shift *link_shift,
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const struct dcn10_link_enc_mask *link_mask)
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{
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struct bp_encoder_cap_info bp_cap_info = {0};
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const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
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enum bp_result result = BP_RESULT_OK;
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struct dcn10_link_encoder *enc10 = &enc21->enc10;
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enc10->base.funcs = &dcn21_link_enc_funcs;
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enc10->base.ctx = init_data->ctx;
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enc10->base.id = init_data->encoder;
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enc10->base.hpd_source = init_data->hpd_source;
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enc10->base.connector = init_data->connector;
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enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
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enc10->base.features = *enc_features;
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enc10->base.transmitter = init_data->transmitter;
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/* set the flag to indicate whether driver poll the I2C data pin
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* while doing the DP sink detect
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*/
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/* if (dal_adapter_service_is_feature_supported(as,
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FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
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enc10->base.features.flags.bits.
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DP_SINK_DETECT_POLL_DATA_PIN = true;*/
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enc10->base.output_signals =
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SIGNAL_TYPE_DVI_SINGLE_LINK |
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SIGNAL_TYPE_DVI_DUAL_LINK |
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SIGNAL_TYPE_LVDS |
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SIGNAL_TYPE_DISPLAY_PORT |
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SIGNAL_TYPE_DISPLAY_PORT_MST |
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SIGNAL_TYPE_EDP |
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SIGNAL_TYPE_HDMI_TYPE_A;
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/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
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* SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
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* SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
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* DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
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* Prefer DIG assignment is decided by board design.
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* For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
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* and VBIOS will filter out 7 UNIPHY for DCE 8.0.
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* By this, adding DIGG should not hurt DCE 8.0.
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* This will let DCE 8.1 share DCE 8.0 as much as possible
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*/
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enc10->link_regs = link_regs;
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enc10->aux_regs = aux_regs;
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enc10->hpd_regs = hpd_regs;
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enc10->link_shift = link_shift;
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enc10->link_mask = link_mask;
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switch (enc10->base.transmitter) {
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case TRANSMITTER_UNIPHY_A:
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enc10->base.preferred_engine = ENGINE_ID_DIGA;
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break;
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case TRANSMITTER_UNIPHY_B:
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enc10->base.preferred_engine = ENGINE_ID_DIGB;
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break;
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case TRANSMITTER_UNIPHY_C:
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enc10->base.preferred_engine = ENGINE_ID_DIGC;
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break;
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case TRANSMITTER_UNIPHY_D:
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enc10->base.preferred_engine = ENGINE_ID_DIGD;
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break;
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case TRANSMITTER_UNIPHY_E:
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enc10->base.preferred_engine = ENGINE_ID_DIGE;
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break;
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case TRANSMITTER_UNIPHY_F:
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enc10->base.preferred_engine = ENGINE_ID_DIGF;
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break;
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case TRANSMITTER_UNIPHY_G:
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enc10->base.preferred_engine = ENGINE_ID_DIGG;
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break;
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default:
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ASSERT_CRITICAL(false);
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enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
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}
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/* default to one to mirror Windows behavior */
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enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
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result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
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enc10->base.id, &bp_cap_info);
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/* Override features with DCE-specific values */
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if (result == BP_RESULT_OK) {
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enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
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bp_cap_info.DP_HBR2_EN;
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enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
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bp_cap_info.DP_HBR3_EN;
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enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
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enc10->base.features.flags.bits.DP_IS_USB_C =
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bp_cap_info.DP_IS_USB_C;
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} else {
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DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
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__func__,
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result);
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}
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if (enc10->base.ctx->dc->debug.hdmi20_disable) {
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enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
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}
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}
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