/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/delay.h>
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#include "dc_bios_types.h"
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#include "dcn20_stream_encoder.h"
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#include "reg_helper.h"
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#include "hw_shared.h"
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#define DC_LOGGER \
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enc1->base.ctx->logger
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#define REG(reg)\
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(enc1->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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enc1->se_shift->field_name, enc1->se_mask->field_name
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#define CTX \
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enc1->base.ctx
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static void enc2_update_hdmi_info_packet(
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struct dcn10_stream_encoder *enc1,
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uint32_t packet_index,
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const struct dc_info_packet *info_packet)
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{
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uint32_t cont, send, line;
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if (info_packet->valid) {
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enc1_update_generic_info_packet(
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enc1,
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packet_index,
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info_packet);
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/* enable transmission of packet(s) -
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* packet transmission begins on the next frame */
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cont = 1;
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/* send packet(s) every frame */
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send = 1;
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/* select line number to send packets on */
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line = 2;
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} else {
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cont = 0;
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send = 0;
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line = 0;
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}
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/* DP_SEC_GSP[x]_LINE_REFERENCE - keep default value REFER_TO_DP_SOF */
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/* choose which generic packet control to use */
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switch (packet_index) {
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case 0:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC0_CONT, cont,
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HDMI_GENERIC0_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
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HDMI_GENERIC0_LINE, line);
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break;
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case 1:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC1_CONT, cont,
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HDMI_GENERIC1_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
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HDMI_GENERIC1_LINE, line);
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break;
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case 2:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC2_CONT, cont,
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HDMI_GENERIC2_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
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HDMI_GENERIC2_LINE, line);
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break;
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case 3:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC3_CONT, cont,
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HDMI_GENERIC3_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
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HDMI_GENERIC3_LINE, line);
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break;
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case 4:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC4_CONT, cont,
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HDMI_GENERIC4_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
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HDMI_GENERIC4_LINE, line);
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break;
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case 5:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC5_CONT, cont,
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HDMI_GENERIC5_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
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HDMI_GENERIC5_LINE, line);
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break;
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case 6:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC6_CONT, cont,
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HDMI_GENERIC6_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
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HDMI_GENERIC6_LINE, line);
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break;
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case 7:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC7_CONT, cont,
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HDMI_GENERIC7_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
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HDMI_GENERIC7_LINE, line);
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break;
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default:
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/* invalid HW packet index */
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DC_LOG_WARNING(
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"Invalid HW packet index: %s()\n",
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__func__);
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return;
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}
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}
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static void enc2_stream_encoder_update_hdmi_info_packets(
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struct stream_encoder *enc,
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const struct encoder_info_frame *info_frame)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
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/* for bring up, disable dp double TODO */
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REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
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/*Always add mandatory packets first followed by optional ones*/
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enc2_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
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enc2_update_hdmi_info_packet(enc1, 1, &info_frame->hfvsif);
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enc2_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
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enc2_update_hdmi_info_packet(enc1, 3, &info_frame->vendor);
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enc2_update_hdmi_info_packet(enc1, 4, &info_frame->spd);
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enc2_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd);
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}
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static void enc2_stream_encoder_stop_hdmi_info_packets(
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struct stream_encoder *enc)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
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/* stop generic packets 0,1 on HDMI */
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REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
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HDMI_GENERIC0_CONT, 0,
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HDMI_GENERIC0_SEND, 0,
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HDMI_GENERIC1_CONT, 0,
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HDMI_GENERIC1_SEND, 0);
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REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0,
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HDMI_GENERIC0_LINE, 0,
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HDMI_GENERIC1_LINE, 0);
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/* stop generic packets 2,3 on HDMI */
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REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
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HDMI_GENERIC2_CONT, 0,
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HDMI_GENERIC2_SEND, 0,
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HDMI_GENERIC3_CONT, 0,
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HDMI_GENERIC3_SEND, 0);
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REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0,
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HDMI_GENERIC2_LINE, 0,
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HDMI_GENERIC3_LINE, 0);
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/* stop generic packets 4,5 on HDMI */
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REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
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HDMI_GENERIC4_CONT, 0,
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HDMI_GENERIC4_SEND, 0,
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HDMI_GENERIC5_CONT, 0,
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HDMI_GENERIC5_SEND, 0);
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REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0,
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HDMI_GENERIC4_LINE, 0,
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HDMI_GENERIC5_LINE, 0);
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/* stop generic packets 6,7 on HDMI */
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REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
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HDMI_GENERIC6_CONT, 0,
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HDMI_GENERIC6_SEND, 0,
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HDMI_GENERIC7_CONT, 0,
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HDMI_GENERIC7_SEND, 0);
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REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0,
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HDMI_GENERIC6_LINE, 0,
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HDMI_GENERIC7_LINE, 0);
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}
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/* Update GSP7 SDP 128 byte long */
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static void enc2_update_gsp7_128_info_packet(
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struct dcn10_stream_encoder *enc1,
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const struct dc_info_packet_128 *info_packet)
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{
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uint32_t i;
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/* TODOFPGA Figure out a proper number for max_retries polling for lock
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* use 50 for now.
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*/
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uint32_t max_retries = 50;
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const uint32_t *content = (const uint32_t *) &info_packet->sb[0];
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ASSERT(info_packet->hb1 == DC_DP_INFOFRAME_TYPE_PPS);
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/* Configure for PPS packet size (128 bytes) */
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REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 1);
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/* We need turn on clock before programming AFMT block*/
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REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
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/* Poll dig_update_lock is not locked -> asic internal signal
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* assumes otg master lock will unlock it
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*/
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/*REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 0, 10, max_retries);*/
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/* Wait for HW/SW GSP memory access conflict to go away */
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REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
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0, 10, max_retries);
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/* Clear HW/SW memory access conflict flag */
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REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
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/* write generic packet header */
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REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, 7);
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REG_SET_4(AFMT_GENERIC_HDR, 0,
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AFMT_GENERIC_HB0, info_packet->hb0,
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AFMT_GENERIC_HB1, info_packet->hb1,
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AFMT_GENERIC_HB2, info_packet->hb2,
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AFMT_GENERIC_HB3, info_packet->hb3);
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/* Write generic packet content 128 bytes long. Four sets are used (indexes 7
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* through 10) to fit 128 bytes.
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*/
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for (i = 0; i < 4; i++) {
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uint32_t packet_index = 7 + i;
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REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, packet_index);
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REG_WRITE(AFMT_GENERIC_0, *content++);
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REG_WRITE(AFMT_GENERIC_1, *content++);
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REG_WRITE(AFMT_GENERIC_2, *content++);
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REG_WRITE(AFMT_GENERIC_3, *content++);
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REG_WRITE(AFMT_GENERIC_4, *content++);
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REG_WRITE(AFMT_GENERIC_5, *content++);
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REG_WRITE(AFMT_GENERIC_6, *content++);
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REG_WRITE(AFMT_GENERIC_7, *content++);
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}
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REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, 1);
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}
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/* Set DSC-related configuration.
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* dsc_mode: 0 disables DSC, other values enable DSC in specified format
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* sc_bytes_per_pixel: Bytes per pixel in u3.28 format
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* dsc_slice_width: Slice width in pixels
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*/
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static void enc2_dp_set_dsc_config(struct stream_encoder *enc,
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enum optc_dsc_mode dsc_mode,
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uint32_t dsc_bytes_per_pixel,
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uint32_t dsc_slice_width)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
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REG_UPDATE_2(DP_DSC_CNTL,
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DP_DSC_MODE, dsc_mode,
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DP_DSC_SLICE_WIDTH, dsc_slice_width);
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REG_SET(DP_DSC_BYTES_PER_PIXEL, 0,
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DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
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}
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static void enc2_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
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bool enable,
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uint8_t *dsc_packed_pps)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
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if (enable) {
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struct dc_info_packet_128 pps_sdp;
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ASSERT(dsc_packed_pps);
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/* Load PPS into infoframe (SDP) registers */
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pps_sdp.valid = true;
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pps_sdp.hb0 = 0;
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pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS;
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pps_sdp.hb2 = 127;
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pps_sdp.hb3 = 0;
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memcpy(&pps_sdp.sb[0], dsc_packed_pps, sizeof(pps_sdp.sb));
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enc2_update_gsp7_128_info_packet(enc1, &pps_sdp);
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/* Enable Generic Stream Packet 7 (GSP) transmission */
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//REG_UPDATE(DP_SEC_CNTL,
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// DP_SEC_GSP7_ENABLE, 1);
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/* SW should make sure VBID[6] update line number is bigger
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* than PPS transmit line number
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*/
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REG_UPDATE(DP_SEC_CNTL6,
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DP_SEC_GSP7_LINE_NUM, 2);
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REG_UPDATE_2(DP_MSA_VBID_MISC,
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DP_VBID6_LINE_REFERENCE, 0,
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DP_VBID6_LINE_NUM, 3);
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/* Send PPS data at the line number specified above.
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* DP spec requires PPS to be sent only when it changes, however since
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* decoder has to be able to handle its change on every frame, we're
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* sending it always (i.e. on every frame) to reduce the chance it'd be
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* missed by decoder. If it turns out required to send PPS only when it
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* changes, we can use DP_SEC_GSP7_SEND register.
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*/
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REG_UPDATE_2(DP_SEC_CNTL,
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DP_SEC_GSP7_ENABLE, 1,
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DP_SEC_STREAM_ENABLE, 1);
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} else {
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/* Disable Generic Stream Packet 7 (GSP) transmission */
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REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, 0);
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REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 0);
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}
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}
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/* this function read dsc related register fields to be logged later in dcn10_log_hw_state
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* into a dcn_dsc_state struct.
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*/
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static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
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//if dsc is enabled, continue to read
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REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
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if (s->dsc_mode) {
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REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width);
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REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp_pps_line_num);
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REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
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REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
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REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable);
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REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
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}
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}
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/* Set Dynamic Metadata-configuration.
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* enable_dme: TRUE: enables Dynamic Metadata Enfine, FALSE: disables DME
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* hubp_requestor_id: HUBP physical instance that is the source of dynamic metadata
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* only needs to be set when enable_dme is TRUE
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* dmdata_mode: dynamic metadata packet type: DP, HDMI, or Dolby Vision
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*
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* Ensure the OTG master update lock is set when changing DME configuration.
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*/
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void enc2_set_dynamic_metadata(struct stream_encoder *enc,
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bool enable_dme,
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uint32_t hubp_requestor_id,
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enum dynamic_metadata_mode dmdata_mode)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
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if (enable_dme) {
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REG_UPDATE_2(DME_CONTROL,
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METADATA_HUBP_REQUESTOR_ID, hubp_requestor_id,
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METADATA_STREAM_TYPE, (dmdata_mode == dmdata_dolby_vision) ? 1 : 0);
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/* Use default line reference DP_SOF for bringup.
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* Should use OTG_SOF for DRR cases
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*/
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if (dmdata_mode == dmdata_dp)
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REG_UPDATE_3(DP_SEC_METADATA_TRANSMISSION,
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DP_SEC_METADATA_PACKET_ENABLE, 1,
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DP_SEC_METADATA_PACKET_LINE_REFERENCE, 0,
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DP_SEC_METADATA_PACKET_LINE, 20);
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else {
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REG_UPDATE_3(HDMI_METADATA_PACKET_CONTROL,
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HDMI_METADATA_PACKET_ENABLE, 1,
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HDMI_METADATA_PACKET_LINE_REFERENCE, 0,
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HDMI_METADATA_PACKET_LINE, 2);
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if (dmdata_mode == dmdata_dolby_vision)
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REG_UPDATE(DIG_FE_CNTL,
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DOLBY_VISION_EN, 1);
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}
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REG_UPDATE(DME_CONTROL,
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METADATA_ENGINE_EN, 1);
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} else {
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REG_UPDATE(DME_CONTROL,
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METADATA_ENGINE_EN, 0);
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if (dmdata_mode == dmdata_dp)
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REG_UPDATE(DP_SEC_METADATA_TRANSMISSION,
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DP_SEC_METADATA_PACKET_ENABLE, 0);
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else {
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REG_UPDATE(HDMI_METADATA_PACKET_CONTROL,
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HDMI_METADATA_PACKET_ENABLE, 0);
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REG_UPDATE(DIG_FE_CNTL,
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DOLBY_VISION_EN, 0);
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}
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}
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}
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static void enc2_stream_encoder_update_dp_info_packets(
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struct stream_encoder *enc,
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const struct encoder_info_frame *info_frame)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
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uint32_t dmdata_packet_enabled = 0;
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enc1_stream_encoder_update_dp_info_packets(enc, info_frame);
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/* check if dynamic metadata packet transmission is enabled */
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REG_GET(DP_SEC_METADATA_TRANSMISSION,
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DP_SEC_METADATA_PACKET_ENABLE, &dmdata_packet_enabled);
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if (dmdata_packet_enabled)
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REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
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}
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static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
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{
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bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
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two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
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&& !timing->dsc_cfg.ycbcr422_simple);
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return two_pix;
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}
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void enc2_stream_encoder_dp_unblank(
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struct stream_encoder *enc,
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const struct encoder_unblank_param *param)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
|
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if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
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uint32_t n_vid = 0x8000;
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uint32_t m_vid;
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uint32_t n_multiply = 0;
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uint64_t m_vid_l = n_vid;
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/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
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if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) {
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/*this logic should be the same in get_pixel_clock_parameters() */
|
n_multiply = 1;
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}
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/* M / N = Fstream / Flink
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* m_vid / n_vid = pixel rate / link rate
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*/
|
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m_vid_l *= param->timing.pix_clk_100hz / 10;
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m_vid_l = div_u64(m_vid_l,
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param->link_settings.link_rate
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* LINK_RATE_REF_FREQ_IN_KHZ);
|
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m_vid = (uint32_t) m_vid_l;
|
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/* enable auto measurement */
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REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
|
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/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
|
* therefore program initial value for Mvid and Nvid
|
*/
|
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REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
|
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REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
|
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REG_UPDATE_2(DP_VID_TIMING,
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DP_VID_M_N_GEN_EN, 1,
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DP_VID_N_MUL, n_multiply);
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}
|
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/* make sure stream is disabled before resetting steer fifo */
|
REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
|
REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
|
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/* set DIG_START to 0x1 to reset FIFO */
|
REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
|
udelay(1);
|
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/* write 0 to take the FIFO out of reset */
|
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REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
|
|
/* switch DP encoder to CRTC data, but reset it the fifo first. It may happen
|
* that it overflows during mode transition, and sometimes doesn't recover.
|
*/
|
REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
|
udelay(10);
|
|
REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
|
|
/* wait 100us for DIG/DP logic to prime
|
* (i.e. a few video lines)
|
*/
|
udelay(100);
|
|
/* the hardware would start sending video at the start of the next DP
|
* frame (i.e. rising edge of the vblank).
|
* NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
|
* register has no effect on enable transition! HW always guarantees
|
* VID_STREAM enable at start of next frame, and this is not
|
* programmable
|
*/
|
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REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
|
}
|
|
static void enc2_dp_set_odm_combine(
|
struct stream_encoder *enc,
|
bool odm_combine)
|
{
|
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
|
|
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);
|
}
|
|
void enc2_stream_encoder_dp_set_stream_attribute(
|
struct stream_encoder *enc,
|
struct dc_crtc_timing *crtc_timing,
|
enum dc_color_space output_color_space,
|
bool use_vsc_sdp_for_colorimetry,
|
uint32_t enable_sdp_splitting)
|
{
|
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
|
|
enc1_stream_encoder_dp_set_stream_attribute(enc,
|
crtc_timing,
|
output_color_space,
|
use_vsc_sdp_for_colorimetry,
|
enable_sdp_splitting);
|
|
REG_UPDATE(DP_SEC_FRAMING4,
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DP_SST_SDP_SPLITTING, enable_sdp_splitting);
|
}
|
|
static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
|
.dp_set_odm_combine =
|
enc2_dp_set_odm_combine,
|
.dp_set_stream_attribute =
|
enc2_stream_encoder_dp_set_stream_attribute,
|
.hdmi_set_stream_attribute =
|
enc1_stream_encoder_hdmi_set_stream_attribute,
|
.dvi_set_stream_attribute =
|
enc1_stream_encoder_dvi_set_stream_attribute,
|
.set_throttled_vcp_size =
|
enc1_stream_encoder_set_throttled_vcp_size,
|
.update_hdmi_info_packets =
|
enc2_stream_encoder_update_hdmi_info_packets,
|
.stop_hdmi_info_packets =
|
enc2_stream_encoder_stop_hdmi_info_packets,
|
.update_dp_info_packets =
|
enc2_stream_encoder_update_dp_info_packets,
|
.send_immediate_sdp_message =
|
enc1_stream_encoder_send_immediate_sdp_message,
|
.stop_dp_info_packets =
|
enc1_stream_encoder_stop_dp_info_packets,
|
.dp_blank =
|
enc1_stream_encoder_dp_blank,
|
.dp_unblank =
|
enc2_stream_encoder_dp_unblank,
|
.audio_mute_control = enc1_se_audio_mute_control,
|
|
.dp_audio_setup = enc1_se_dp_audio_setup,
|
.dp_audio_enable = enc1_se_dp_audio_enable,
|
.dp_audio_disable = enc1_se_dp_audio_disable,
|
|
.hdmi_audio_setup = enc1_se_hdmi_audio_setup,
|
.hdmi_audio_disable = enc1_se_hdmi_audio_disable,
|
.setup_stereo_sync = enc1_setup_stereo_sync,
|
.set_avmute = enc1_stream_encoder_set_avmute,
|
.dig_connect_to_otg = enc1_dig_connect_to_otg,
|
.dig_source_otg = enc1_dig_source_otg,
|
|
.dp_get_pixel_format =
|
enc1_stream_encoder_dp_get_pixel_format,
|
|
.enc_read_state = enc2_read_state,
|
.dp_set_dsc_config = enc2_dp_set_dsc_config,
|
.dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet,
|
.set_dynamic_metadata = enc2_set_dynamic_metadata,
|
.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
|
};
|
|
void dcn20_stream_encoder_construct(
|
struct dcn10_stream_encoder *enc1,
|
struct dc_context *ctx,
|
struct dc_bios *bp,
|
enum engine_id eng_id,
|
const struct dcn10_stream_enc_registers *regs,
|
const struct dcn10_stream_encoder_shift *se_shift,
|
const struct dcn10_stream_encoder_mask *se_mask)
|
{
|
enc1->base.funcs = &dcn20_str_enc_funcs;
|
enc1->base.ctx = ctx;
|
enc1->base.id = eng_id;
|
enc1->base.bp = bp;
|
enc1->regs = regs;
|
enc1->se_shift = se_shift;
|
enc1->se_mask = se_mask;
|
enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA;
|
}
|
