/* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_CLOCK_SOURCE_DCE_H__
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#define __DC_CLOCK_SOURCE_DCE_H__
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#include "../inc/clock_source.h"
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#define TO_DCE110_CLK_SRC(clk_src)\
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container_of(clk_src, struct dce110_clk_src, base)
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#define CS_COMMON_REG_LIST_DCE_100_110(id) \
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SRI(RESYNC_CNTL, PIXCLK, id), \
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SRI(PLL_CNTL, BPHYC_PLL, id)
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#define CS_COMMON_REG_LIST_DCE_80(id) \
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SRI(RESYNC_CNTL, PIXCLK, id), \
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SRI(PLL_CNTL, DCCG_PLL, id)
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#define CS_COMMON_REG_LIST_DCE_112(id) \
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SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
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#define CS_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
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CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\
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CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\
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CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\
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CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
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#define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
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CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
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CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
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#define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \
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SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
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SRII(PHASE, DP_DTO, 0),\
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SRII(PHASE, DP_DTO, 1),\
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SRII(PHASE, DP_DTO, 2),\
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SRII(PHASE, DP_DTO, 3),\
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SRII(PHASE, DP_DTO, 4),\
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SRII(PHASE, DP_DTO, 5),\
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SRII(MODULO, DP_DTO, 0),\
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SRII(MODULO, DP_DTO, 1),\
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SRII(MODULO, DP_DTO, 2),\
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SRII(MODULO, DP_DTO, 3),\
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SRII(MODULO, DP_DTO, 4),\
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SRII(MODULO, DP_DTO, 5),\
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SRII(PIXEL_RATE_CNTL, OTG, 0),\
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SRII(PIXEL_RATE_CNTL, OTG, 1),\
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SRII(PIXEL_RATE_CNTL, OTG, 2),\
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SRII(PIXEL_RATE_CNTL, OTG, 3),\
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SRII(PIXEL_RATE_CNTL, OTG, 4),\
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SRII(PIXEL_RATE_CNTL, OTG, 5)
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#define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
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SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
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SRII(PHASE, DP_DTO, 0),\
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SRII(PHASE, DP_DTO, 1),\
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SRII(PHASE, DP_DTO, 2),\
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SRII(PHASE, DP_DTO, 3),\
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SRII(MODULO, DP_DTO, 0),\
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SRII(MODULO, DP_DTO, 1),\
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SRII(MODULO, DP_DTO, 2),\
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SRII(MODULO, DP_DTO, 3),\
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SRII(PIXEL_RATE_CNTL, OTG, 0),\
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SRII(PIXEL_RATE_CNTL, OTG, 1),\
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SRII(PIXEL_RATE_CNTL, OTG, 2),\
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SRII(PIXEL_RATE_CNTL, OTG, 3)
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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#define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \
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SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
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SRII(PHASE, DP_DTO, 0),\
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SRII(PHASE, DP_DTO, 1),\
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SRII(PHASE, DP_DTO, 2),\
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SRII(PHASE, DP_DTO, 3),\
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SRII(MODULO, DP_DTO, 0),\
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SRII(MODULO, DP_DTO, 1),\
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SRII(MODULO, DP_DTO, 2),\
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SRII(MODULO, DP_DTO, 3),\
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SRII(PIXEL_RATE_CNTL, OTG, 0),\
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SRII(PIXEL_RATE_CNTL, OTG, 1),\
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SRII(PIXEL_RATE_CNTL, OTG, 2),\
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SRII(PIXEL_RATE_CNTL, OTG, 3)
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#endif
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#define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
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CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
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CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
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CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
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CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
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SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
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SRII(PHASE, DP_DTO, 0),\
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SRII(PHASE, DP_DTO, 1),\
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SRII(PHASE, DP_DTO, 2),\
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SRII(PHASE, DP_DTO, 3),\
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SRII(MODULO, DP_DTO, 0),\
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SRII(MODULO, DP_DTO, 1),\
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SRII(MODULO, DP_DTO, 2),\
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SRII(MODULO, DP_DTO, 3),\
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SRII(PIXEL_RATE_CNTL, OTG, 0), \
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SRII(PIXEL_RATE_CNTL, OTG, 1), \
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SRII(PIXEL_RATE_CNTL, OTG, 2), \
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SRII(PIXEL_RATE_CNTL, OTG, 3)
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#define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
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CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
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CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
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CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
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CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
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#endif
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#define CS_REG_FIELD_LIST(type) \
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type PLL_REF_DIV_SRC; \
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type DCCG_DEEP_COLOR_CNTL1; \
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type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \
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type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \
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type PLL_POST_DIV_PIXCLK; \
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type PLL_REF_DIV; \
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type DP_DTO0_PHASE; \
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type DP_DTO0_MODULO; \
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type DP_DTO0_ENABLE;
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struct dce110_clk_src_shift {
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CS_REG_FIELD_LIST(uint8_t)
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};
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struct dce110_clk_src_mask{
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CS_REG_FIELD_LIST(uint32_t)
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};
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struct dce110_clk_src_regs {
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uint32_t RESYNC_CNTL;
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uint32_t PIXCLK_RESYNC_CNTL;
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uint32_t PLL_CNTL;
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/* below are for DTO.
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* todo: should probably use different struct to not waste space
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*/
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uint32_t PHASE[MAX_PIPES];
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uint32_t MODULO[MAX_PIPES];
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uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
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};
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struct dce110_clk_src {
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struct clock_source base;
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const struct dce110_clk_src_regs *regs;
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const struct dce110_clk_src_mask *cs_mask;
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const struct dce110_clk_src_shift *cs_shift;
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struct dc_bios *bios;
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struct spread_spectrum_data *dp_ss_params;
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uint32_t dp_ss_params_cnt;
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struct spread_spectrum_data *hdmi_ss_params;
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uint32_t hdmi_ss_params_cnt;
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struct spread_spectrum_data *dvi_ss_params;
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uint32_t dvi_ss_params_cnt;
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struct spread_spectrum_data *lvds_ss_params;
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uint32_t lvds_ss_params_cnt;
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uint32_t ext_clk_khz;
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uint32_t ref_freq_khz;
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struct calc_pll_clock_source calc_pll;
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struct calc_pll_clock_source calc_pll_hdmi;
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};
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bool dce110_clk_src_construct(
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struct dce110_clk_src *clk_src,
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struct dc_context *ctx,
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struct dc_bios *bios,
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enum clock_source_id,
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const struct dce110_clk_src_regs *regs,
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const struct dce110_clk_src_shift *cs_shift,
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const struct dce110_clk_src_mask *cs_mask);
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bool dce112_clk_src_construct(
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struct dce110_clk_src *clk_src,
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struct dc_context *ctx,
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struct dc_bios *bios,
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enum clock_source_id id,
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const struct dce110_clk_src_regs *regs,
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const struct dce110_clk_src_shift *cs_shift,
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const struct dce110_clk_src_mask *cs_mask);
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bool dcn20_clk_src_construct(
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struct dce110_clk_src *clk_src,
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struct dc_context *ctx,
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struct dc_bios *bios,
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enum clock_source_id id,
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const struct dce110_clk_src_regs *regs,
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const struct dce110_clk_src_shift *cs_shift,
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const struct dce110_clk_src_mask *cs_mask);
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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bool dcn3_clk_src_construct(
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struct dce110_clk_src *clk_src,
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struct dc_context *ctx,
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struct dc_bios *bios,
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enum clock_source_id id,
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const struct dce110_clk_src_regs *regs,
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const struct dce110_clk_src_shift *cs_shift,
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const struct dce110_clk_src_mask *cs_mask);
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#endif
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/* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
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struct pixel_rate_range_table_entry {
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unsigned int range_min_khz;
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unsigned int range_max_khz;
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unsigned int target_pixel_rate_khz;
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unsigned short mult_factor;
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unsigned short div_factor;
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};
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[];
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const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
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unsigned int pixel_rate_khz);
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#endif
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#endif
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