/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/slab.h>
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#include "dce_clk_mgr.h"
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#include "reg_helper.h"
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#include "dmcu.h"
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#include "core_types.h"
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#include "dal_asic_id.h"
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#define TO_DCE_CLK_MGR(clocks)\
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container_of(clocks, struct dce_clk_mgr, base)
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#define REG(reg) \
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(clk_mgr_dce->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name
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#define CTX \
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clk_mgr_dce->base.ctx
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#define DC_LOGGER \
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clk_mgr->ctx->logger
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/* Max clock values for each state indexed by "enum clocks_state": */
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static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
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/* ClocksStateInvalid - should not be used */
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{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
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/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
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{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
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/* ClocksStateLow */
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{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
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/* ClocksStateNominal */
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{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
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/* ClocksStatePerformance */
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{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
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static const struct state_dependent_clocks dce110_max_clks_by_state[] = {
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/*ClocksStateInvalid - should not be used*/
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{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
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/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
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{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
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/*ClocksStateLow*/
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{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
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/*ClocksStateNominal*/
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{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
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/*ClocksStatePerformance*/
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{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
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static const struct state_dependent_clocks dce112_max_clks_by_state[] = {
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/*ClocksStateInvalid - should not be used*/
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{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
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/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
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{ .display_clk_khz = 389189, .pixel_clk_khz = 346672 },
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/*ClocksStateLow*/
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{ .display_clk_khz = 459000, .pixel_clk_khz = 400000 },
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/*ClocksStateNominal*/
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{ .display_clk_khz = 667000, .pixel_clk_khz = 600000 },
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/*ClocksStatePerformance*/
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{ .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
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static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
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/*ClocksStateInvalid - should not be used*/
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{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
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/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
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{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
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/*ClocksStateLow*/
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{ .display_clk_khz = 460000, .pixel_clk_khz = 400000 },
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/*ClocksStateNominal*/
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{ .display_clk_khz = 670000, .pixel_clk_khz = 600000 },
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/*ClocksStatePerformance*/
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{ .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
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int dentist_get_divider_from_did(int did)
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{
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if (did < DENTIST_BASE_DID_1)
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did = DENTIST_BASE_DID_1;
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if (did > DENTIST_MAX_DID)
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did = DENTIST_MAX_DID;
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if (did < DENTIST_BASE_DID_2) {
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return DENTIST_DIVIDER_RANGE_1_START + DENTIST_DIVIDER_RANGE_1_STEP
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* (did - DENTIST_BASE_DID_1);
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} else if (did < DENTIST_BASE_DID_3) {
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return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP
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* (did - DENTIST_BASE_DID_2);
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} else if (did < DENTIST_BASE_DID_4) {
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return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP
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* (did - DENTIST_BASE_DID_3);
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} else {
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return DENTIST_DIVIDER_RANGE_4_START + DENTIST_DIVIDER_RANGE_4_STEP
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* (did - DENTIST_BASE_DID_4);
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}
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}
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/* SW will adjust DP REF Clock average value for all purposes
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* (DP DTO / DP Audio DTO and DP GTC)
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if clock is spread for all cases:
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-if SS enabled on DP Ref clock and HW de-spreading enabled with SW
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calculations for DS_INCR/DS_MODULO (this is planned to be default case)
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-if SS enabled on DP Ref clock and HW de-spreading enabled with HW
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calculations (not planned to be used, but average clock should still
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be valid)
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-if SS enabled on DP Ref clock and HW de-spreading disabled
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(should not be case with CIK) then SW should program all rates
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generated according to average value (case as with previous ASICs)
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*/
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static int clk_mgr_adjust_dp_ref_freq_for_ss(struct dce_clk_mgr *clk_mgr_dce, int dp_ref_clk_khz)
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{
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if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) {
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struct fixed31_32 ss_percentage = dc_fixpt_div_int(
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dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage,
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clk_mgr_dce->dprefclk_ss_divider), 200);
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struct fixed31_32 adj_dp_ref_clk_khz;
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ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage);
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adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);
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dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
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}
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return dp_ref_clk_khz;
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}
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static int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr)
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{
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struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
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int dprefclk_wdivider;
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int dprefclk_src_sel;
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int dp_ref_clk_khz = 600000;
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int target_div;
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/* ASSERT DP Reference Clock source is from DFS*/
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REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
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ASSERT(dprefclk_src_sel == 0);
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/* Read the mmDENTIST_DISPCLK_CNTL to get the currently
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* programmed DID DENTIST_DPREFCLK_WDIVIDER*/
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REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
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/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
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target_div = dentist_get_divider_from_did(dprefclk_wdivider);
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/* Calculate the current DFS clock, in kHz.*/
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dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
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* clk_mgr_dce->dentist_vco_freq_khz) / target_div;
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return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, dp_ref_clk_khz);
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}
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int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr)
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{
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struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
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return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz);
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}
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/* unit: in_khz before mode set, get pixel clock from context. ASIC register
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* may not be programmed yet
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*/
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static uint32_t get_max_pixel_clock_for_all_paths(struct dc_state *context)
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{
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uint32_t max_pix_clk = 0;
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int i;
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for (i = 0; i < MAX_PIPES; i++) {
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
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if (pipe_ctx->stream == NULL)
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continue;
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/* do not check under lay */
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if (pipe_ctx->top_pipe)
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continue;
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if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
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max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
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/* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS
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* logic for HBR3 still needs Nominal (0.8V) on VDDC rail
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*/
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if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
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pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
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max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
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}
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return max_pix_clk;
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}
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static enum dm_pp_clocks_state dce_get_required_clocks_state(
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struct clk_mgr *clk_mgr,
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struct dc_state *context)
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{
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struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
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int i;
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enum dm_pp_clocks_state low_req_clk;
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int max_pix_clk = get_max_pixel_clock_for_all_paths(context);
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/* Iterate from highest supported to lowest valid state, and update
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* lowest RequiredState with the lowest state that satisfies
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* all required clocks
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*/
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for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
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if (context->bw_ctx.bw.dce.dispclk_khz >
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clk_mgr_dce->max_clks_by_state[i].display_clk_khz
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|| max_pix_clk >
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clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz)
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break;
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low_req_clk = i + 1;
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if (low_req_clk > clk_mgr_dce->max_clks_state) {
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/* set max clock state for high phyclock, invalid on exceeding display clock */
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if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz
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< context->bw_ctx.bw.dce.dispclk_khz)
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low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
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else
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low_req_clk = clk_mgr_dce->max_clks_state;
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}
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return low_req_clk;
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}
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static int dce_set_clock(
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struct clk_mgr *clk_mgr,
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int requested_clk_khz)
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{
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struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
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struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
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struct dc_bios *bp = clk_mgr->ctx->dc_bios;
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int actual_clock = requested_clk_khz;
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struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
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/* Make sure requested clock isn't lower than minimum threshold*/
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if (requested_clk_khz > 0)
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requested_clk_khz = max(requested_clk_khz,
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clk_mgr_dce->dentist_vco_freq_khz / 64);
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/* Prepare to program display clock*/
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pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
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pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
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if (clk_mgr_dce->dfs_bypass_active)
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pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;
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bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
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if (clk_mgr_dce->dfs_bypass_active) {
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/* Cache the fixed display clock*/
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clk_mgr_dce->dfs_bypass_disp_clk =
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pxl_clk_params.dfs_bypass_display_clock;
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actual_clock = pxl_clk_params.dfs_bypass_display_clock;
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}
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/* from power down, we need mark the clock state as ClocksStateNominal
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* from HWReset, so when resume we will call pplib voltage regulator.*/
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if (requested_clk_khz == 0)
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clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
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if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
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dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
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return actual_clock;
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}
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int dce112_set_clock(struct clk_mgr *clk_mgr, int requested_clk_khz)
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{
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struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
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struct bp_set_dce_clock_parameters dce_clk_params;
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struct dc_bios *bp = clk_mgr->ctx->dc_bios;
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struct dc *core_dc = clk_mgr->ctx->dc;
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struct dmcu *dmcu = core_dc->res_pool->dmcu;
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int actual_clock = requested_clk_khz;
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/* Prepare to program display clock*/
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memset(&dce_clk_params, 0, sizeof(dce_clk_params));
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/* Make sure requested clock isn't lower than minimum threshold*/
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if (requested_clk_khz > 0)
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requested_clk_khz = max(requested_clk_khz,
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clk_mgr_dce->dentist_vco_freq_khz / 62);
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dce_clk_params.target_clock_frequency = requested_clk_khz;
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dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
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dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
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bp->funcs->set_dce_clock(bp, &dce_clk_params);
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actual_clock = dce_clk_params.target_clock_frequency;
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/* from power down, we need mark the clock state as ClocksStateNominal
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* from HWReset, so when resume we will call pplib voltage regulator.*/
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if (requested_clk_khz == 0)
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clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
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/*Program DP ref Clock*/
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/*VBIOS will determine DPREFCLK frequency, so we don't set it*/
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dce_clk_params.target_clock_frequency = 0;
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dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
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if (!ASICREV_IS_VEGA20_P(clk_mgr->ctx->asic_id.hw_internal_rev))
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dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
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(dce_clk_params.pll_id ==
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CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
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else
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dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
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bp->funcs->set_dce_clock(bp, &dce_clk_params);
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if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
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if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
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if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
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dmcu->funcs->set_psr_wait_loop(dmcu,
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actual_clock / 1000 / 7);
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}
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}
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clk_mgr_dce->dfs_bypass_disp_clk = actual_clock;
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return actual_clock;
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}
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static void dce_clock_read_integrated_info(struct dce_clk_mgr *clk_mgr_dce)
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{
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struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
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struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
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struct integrated_info info = { { { 0 } } };
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struct dc_firmware_info fw_info = { { 0 } };
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int i;
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if (bp->integrated_info)
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info = *bp->integrated_info;
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clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq;
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if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
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bp->funcs->get_firmware_info(bp, &fw_info);
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clk_mgr_dce->dentist_vco_freq_khz =
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fw_info.smu_gpu_pll_output_freq;
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if (clk_mgr_dce->dentist_vco_freq_khz == 0)
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clk_mgr_dce->dentist_vco_freq_khz = 3600000;
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}
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/*update the maximum display clock for each power state*/
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for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
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enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
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switch (i) {
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case 0:
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clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
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break;
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case 1:
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clk_state = DM_PP_CLOCKS_STATE_LOW;
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break;
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case 2:
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clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
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break;
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case 3:
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clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
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break;
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default:
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clk_state = DM_PP_CLOCKS_STATE_INVALID;
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break;
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}
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/*Do not allow bad VBIOS/SBIOS to override with invalid values,
|
* check for > 100MHz*/
|
if (info.disp_clk_voltage[i].max_supported_clk >= 100000)
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clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
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info.disp_clk_voltage[i].max_supported_clk;
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}
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if (!debug->disable_dfs_bypass && bp->integrated_info)
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if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
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clk_mgr_dce->dfs_bypass_enabled = true;
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}
|
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void dce_clock_read_ss_info(struct dce_clk_mgr *clk_mgr_dce)
|
{
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struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
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int ss_info_num = bp->funcs->get_ss_entry_number(
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bp, AS_SIGNAL_TYPE_GPU_PLL);
|
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if (ss_info_num) {
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struct spread_spectrum_info info = { { 0 } };
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enum bp_result result = bp->funcs->get_spread_spectrum_info(
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bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
|
|
/* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
|
* even if SS not enabled and in that case
|
* SSInfo.spreadSpectrumPercentage !=0 would be sign
|
* that SS is enabled
|
*/
|
if (result == BP_RESULT_OK &&
|
info.spread_spectrum_percentage != 0) {
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clk_mgr_dce->ss_on_dprefclk = true;
|
clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
|
|
if (info.type.CENTER_MODE == 0) {
|
/* TODO: Currently for DP Reference clock we
|
* need only SS percentage for
|
* downspread */
|
clk_mgr_dce->dprefclk_ss_percentage =
|
info.spread_spectrum_percentage;
|
}
|
|
return;
|
}
|
|
result = bp->funcs->get_spread_spectrum_info(
|
bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info);
|
|
/* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS
|
* even if SS not enabled and in that case
|
* SSInfo.spreadSpectrumPercentage !=0 would be sign
|
* that SS is enabled
|
*/
|
if (result == BP_RESULT_OK &&
|
info.spread_spectrum_percentage != 0) {
|
clk_mgr_dce->ss_on_dprefclk = true;
|
clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
|
|
if (info.type.CENTER_MODE == 0) {
|
/* Currently for DP Reference clock we
|
* need only SS percentage for
|
* downspread */
|
clk_mgr_dce->dprefclk_ss_percentage =
|
info.spread_spectrum_percentage;
|
}
|
}
|
}
|
}
|
|
/**
|
* dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
|
* @clk_mgr: clock manager base structure
|
*
|
* Reads from VBIOS the XGMI spread spectrum info and saves it within
|
* the dce clock manager. This operation will overwrite the existing dprefclk
|
* SS values if the vBIOS query succeeds. Otherwise, it does nothing. It also
|
* sets the ->xgmi_enabled flag.
|
*/
|
void dce121_clock_patch_xgmi_ss_info(struct clk_mgr *clk_mgr)
|
{
|
struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
|
enum bp_result result;
|
struct spread_spectrum_info info = { { 0 } };
|
struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
|
|
clk_mgr_dce->xgmi_enabled = false;
|
|
result = bp->funcs->get_spread_spectrum_info(bp, AS_SIGNAL_TYPE_XGMI,
|
0, &info);
|
if (result == BP_RESULT_OK && info.spread_spectrum_percentage != 0) {
|
clk_mgr_dce->xgmi_enabled = true;
|
clk_mgr_dce->ss_on_dprefclk = true;
|
clk_mgr_dce->dprefclk_ss_divider =
|
info.spread_percentage_divider;
|
|
if (info.type.CENTER_MODE == 0) {
|
/* Currently for DP Reference clock we
|
* need only SS percentage for
|
* downspread */
|
clk_mgr_dce->dprefclk_ss_percentage =
|
info.spread_spectrum_percentage;
|
}
|
}
|
}
|
|
void dce110_fill_display_configs(
|
const struct dc_state *context,
|
struct dm_pp_display_configuration *pp_display_cfg)
|
{
|
int j;
|
int num_cfgs = 0;
|
|
for (j = 0; j < context->stream_count; j++) {
|
int k;
|
|
const struct dc_stream_state *stream = context->streams[j];
|
struct dm_pp_single_disp_config *cfg =
|
&pp_display_cfg->disp_configs[num_cfgs];
|
const struct pipe_ctx *pipe_ctx = NULL;
|
|
for (k = 0; k < MAX_PIPES; k++)
|
if (stream == context->res_ctx.pipe_ctx[k].stream) {
|
pipe_ctx = &context->res_ctx.pipe_ctx[k];
|
break;
|
}
|
|
ASSERT(pipe_ctx != NULL);
|
|
/* only notify active stream */
|
if (stream->dpms_off)
|
continue;
|
|
num_cfgs++;
|
cfg->signal = pipe_ctx->stream->signal;
|
cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
|
cfg->src_height = stream->src.height;
|
cfg->src_width = stream->src.width;
|
cfg->ddi_channel_mapping =
|
stream->link->ddi_channel_mapping.raw;
|
cfg->transmitter =
|
stream->link->link_enc->transmitter;
|
cfg->link_settings.lane_count =
|
stream->link->cur_link_settings.lane_count;
|
cfg->link_settings.link_rate =
|
stream->link->cur_link_settings.link_rate;
|
cfg->link_settings.link_spread =
|
stream->link->cur_link_settings.link_spread;
|
cfg->sym_clock = stream->phy_pix_clk;
|
/* Round v_refresh*/
|
cfg->v_refresh = stream->timing.pix_clk_100hz * 100;
|
cfg->v_refresh /= stream->timing.h_total;
|
cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
|
/ stream->timing.v_total;
|
}
|
|
pp_display_cfg->display_count = num_cfgs;
|
}
|
|
static uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
|
{
|
uint8_t j;
|
uint32_t min_vertical_blank_time = -1;
|
|
for (j = 0; j < context->stream_count; j++) {
|
struct dc_stream_state *stream = context->streams[j];
|
uint32_t vertical_blank_in_pixels = 0;
|
uint32_t vertical_blank_time = 0;
|
|
vertical_blank_in_pixels = stream->timing.h_total *
|
(stream->timing.v_total
|
- stream->timing.v_addressable);
|
|
vertical_blank_time = vertical_blank_in_pixels
|
* 10000 / stream->timing.pix_clk_100hz;
|
|
if (min_vertical_blank_time > vertical_blank_time)
|
min_vertical_blank_time = vertical_blank_time;
|
}
|
|
return min_vertical_blank_time;
|
}
|
|
static int determine_sclk_from_bounding_box(
|
const struct dc *dc,
|
int required_sclk)
|
{
|
int i;
|
|
/*
|
* Some asics do not give us sclk levels, so we just report the actual
|
* required sclk
|
*/
|
if (dc->sclk_lvls.num_levels == 0)
|
return required_sclk;
|
|
for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
|
if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
|
return dc->sclk_lvls.clocks_in_khz[i];
|
}
|
/*
|
* even maximum level could not satisfy requirement, this
|
* is unexpected at this stage, should have been caught at
|
* validation time
|
*/
|
ASSERT(0);
|
return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
|
}
|
|
static void dce_pplib_apply_display_requirements(
|
struct dc *dc,
|
struct dc_state *context)
|
{
|
struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
|
|
pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
|
|
dce110_fill_display_configs(context, pp_display_cfg);
|
|
if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
|
dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
|
}
|
|
static void dce11_pplib_apply_display_requirements(
|
struct dc *dc,
|
struct dc_state *context)
|
{
|
struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
|
|
pp_display_cfg->all_displays_in_sync =
|
context->bw_ctx.bw.dce.all_displays_in_sync;
|
pp_display_cfg->nb_pstate_switch_disable =
|
context->bw_ctx.bw.dce.nbp_state_change_enable == false;
|
pp_display_cfg->cpu_cc6_disable =
|
context->bw_ctx.bw.dce.cpuc_state_change_enable == false;
|
pp_display_cfg->cpu_pstate_disable =
|
context->bw_ctx.bw.dce.cpup_state_change_enable == false;
|
pp_display_cfg->cpu_pstate_separation_time =
|
context->bw_ctx.bw.dce.blackout_recovery_time_us;
|
|
pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
|
/ MEMORY_TYPE_MULTIPLIER_CZ;
|
|
pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
|
dc,
|
context->bw_ctx.bw.dce.sclk_khz);
|
|
/*
|
* As workaround for >4x4K lightup set dcfclock to min_engine_clock value.
|
* This is not required for less than 5 displays,
|
* thus don't request decfclk in dc to avoid impact
|
* on power saving.
|
*
|
*/
|
pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4)?
|
pp_display_cfg->min_engine_clock_khz : 0;
|
|
pp_display_cfg->min_engine_clock_deep_sleep_khz
|
= context->bw_ctx.bw.dce.sclk_deep_sleep_khz;
|
|
pp_display_cfg->avail_mclk_switch_time_us =
|
dce110_get_min_vblank_time_us(context);
|
/* TODO: dce11.2*/
|
pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
|
|
pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz;
|
|
dce110_fill_display_configs(context, pp_display_cfg);
|
|
/* TODO: is this still applicable?*/
|
if (pp_display_cfg->display_count == 1) {
|
const struct dc_crtc_timing *timing =
|
&context->streams[0]->timing;
|
|
pp_display_cfg->crtc_index =
|
pp_display_cfg->disp_configs[0].pipe_idx;
|
pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
|
}
|
|
if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
|
dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
|
}
|
|
static void dce_update_clocks(struct clk_mgr *clk_mgr,
|
struct dc_state *context,
|
bool safe_to_lower)
|
{
|
struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
|
struct dm_pp_power_level_change_request level_change_req;
|
int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
|
|
/*TODO: W/A for dal3 linux, investigate why this works */
|
if (!clk_mgr_dce->dfs_bypass_active)
|
patched_disp_clk = patched_disp_clk * 115 / 100;
|
|
level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
|
/* get max clock state from PPLIB */
|
if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
|
|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
|
if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
|
clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
|
}
|
|
if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
|
patched_disp_clk = dce_set_clock(clk_mgr, patched_disp_clk);
|
clk_mgr->clks.dispclk_khz = patched_disp_clk;
|
}
|
dce_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
|
}
|
|
static void dce11_update_clocks(struct clk_mgr *clk_mgr,
|
struct dc_state *context,
|
bool safe_to_lower)
|
{
|
struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
|
struct dm_pp_power_level_change_request level_change_req;
|
int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
|
|
/*TODO: W/A for dal3 linux, investigate why this works */
|
if (!clk_mgr_dce->dfs_bypass_active)
|
patched_disp_clk = patched_disp_clk * 115 / 100;
|
|
level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
|
/* get max clock state from PPLIB */
|
if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
|
|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
|
if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
|
clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
|
}
|
|
if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
|
context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr, patched_disp_clk);
|
clk_mgr->clks.dispclk_khz = patched_disp_clk;
|
}
|
dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
|
}
|
|
static void dce112_update_clocks(struct clk_mgr *clk_mgr,
|
struct dc_state *context,
|
bool safe_to_lower)
|
{
|
struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
|
struct dm_pp_power_level_change_request level_change_req;
|
int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
|
|
/*TODO: W/A for dal3 linux, investigate why this works */
|
if (!clk_mgr_dce->dfs_bypass_active)
|
patched_disp_clk = patched_disp_clk * 115 / 100;
|
|
level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
|
/* get max clock state from PPLIB */
|
if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
|
|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
|
if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
|
clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
|
}
|
|
if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
|
patched_disp_clk = dce112_set_clock(clk_mgr, patched_disp_clk);
|
clk_mgr->clks.dispclk_khz = patched_disp_clk;
|
}
|
dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
|
}
|
|
static void dce12_update_clocks(struct clk_mgr *clk_mgr,
|
struct dc_state *context,
|
bool safe_to_lower)
|
{
|
struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
|
struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
|
int max_pix_clk = get_max_pixel_clock_for_all_paths(context);
|
int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
|
|
/*TODO: W/A for dal3 linux, investigate why this works */
|
if (!clk_mgr_dce->dfs_bypass_active)
|
patched_disp_clk = patched_disp_clk * 115 / 100;
|
|
if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
|
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
|
/*
|
* When xGMI is enabled, the display clk needs to be adjusted
|
* with the WAFL link's SS percentage.
|
*/
|
if (clk_mgr_dce->xgmi_enabled)
|
patched_disp_clk = clk_mgr_adjust_dp_ref_freq_for_ss(
|
clk_mgr_dce, patched_disp_clk);
|
clock_voltage_req.clocks_in_khz = patched_disp_clk;
|
clk_mgr->clks.dispclk_khz = dce112_set_clock(clk_mgr, patched_disp_clk);
|
|
dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req);
|
}
|
|
if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr->clks.phyclk_khz)) {
|
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK;
|
clock_voltage_req.clocks_in_khz = max_pix_clk;
|
clk_mgr->clks.phyclk_khz = max_pix_clk;
|
|
dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req);
|
}
|
dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
|
}
|
|
static const struct clk_mgr_funcs dce120_funcs = {
|
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
|
.update_clocks = dce12_update_clocks
|
};
|
|
static const struct clk_mgr_funcs dce112_funcs = {
|
.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
|
.update_clocks = dce112_update_clocks
|
};
|
|
static const struct clk_mgr_funcs dce110_funcs = {
|
.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
|
.update_clocks = dce11_update_clocks,
|
};
|
|
static const struct clk_mgr_funcs dce_funcs = {
|
.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
|
.update_clocks = dce_update_clocks
|
};
|
|
static void dce_clk_mgr_construct(
|
struct dce_clk_mgr *clk_mgr_dce,
|
struct dc_context *ctx,
|
const struct clk_mgr_registers *regs,
|
const struct clk_mgr_shift *clk_shift,
|
const struct clk_mgr_mask *clk_mask)
|
{
|
struct clk_mgr *base = &clk_mgr_dce->base;
|
struct dm_pp_static_clock_info static_clk_info = {0};
|
|
base->ctx = ctx;
|
base->funcs = &dce_funcs;
|
|
clk_mgr_dce->regs = regs;
|
clk_mgr_dce->clk_mgr_shift = clk_shift;
|
clk_mgr_dce->clk_mgr_mask = clk_mask;
|
|
clk_mgr_dce->dfs_bypass_disp_clk = 0;
|
|
clk_mgr_dce->dprefclk_ss_percentage = 0;
|
clk_mgr_dce->dprefclk_ss_divider = 1000;
|
clk_mgr_dce->ss_on_dprefclk = false;
|
|
|
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
|
clk_mgr_dce->max_clks_state = static_clk_info.max_clocks_state;
|
else
|
clk_mgr_dce->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
|
clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
|
|
dce_clock_read_integrated_info(clk_mgr_dce);
|
dce_clock_read_ss_info(clk_mgr_dce);
|
}
|
|
struct clk_mgr *dce_clk_mgr_create(
|
struct dc_context *ctx,
|
const struct clk_mgr_registers *regs,
|
const struct clk_mgr_shift *clk_shift,
|
const struct clk_mgr_mask *clk_mask)
|
{
|
struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
|
|
if (clk_mgr_dce == NULL) {
|
BREAK_TO_DEBUGGER();
|
return NULL;
|
}
|
|
memcpy(clk_mgr_dce->max_clks_by_state,
|
dce80_max_clks_by_state,
|
sizeof(dce80_max_clks_by_state));
|
|
dce_clk_mgr_construct(
|
clk_mgr_dce, ctx, regs, clk_shift, clk_mask);
|
|
return &clk_mgr_dce->base;
|
}
|
|
struct clk_mgr *dce110_clk_mgr_create(
|
struct dc_context *ctx,
|
const struct clk_mgr_registers *regs,
|
const struct clk_mgr_shift *clk_shift,
|
const struct clk_mgr_mask *clk_mask)
|
{
|
struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
|
|
if (clk_mgr_dce == NULL) {
|
BREAK_TO_DEBUGGER();
|
return NULL;
|
}
|
|
memcpy(clk_mgr_dce->max_clks_by_state,
|
dce110_max_clks_by_state,
|
sizeof(dce110_max_clks_by_state));
|
|
dce_clk_mgr_construct(
|
clk_mgr_dce, ctx, regs, clk_shift, clk_mask);
|
|
clk_mgr_dce->base.funcs = &dce110_funcs;
|
|
return &clk_mgr_dce->base;
|
}
|
|
struct clk_mgr *dce112_clk_mgr_create(
|
struct dc_context *ctx,
|
const struct clk_mgr_registers *regs,
|
const struct clk_mgr_shift *clk_shift,
|
const struct clk_mgr_mask *clk_mask)
|
{
|
struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
|
|
if (clk_mgr_dce == NULL) {
|
BREAK_TO_DEBUGGER();
|
return NULL;
|
}
|
|
memcpy(clk_mgr_dce->max_clks_by_state,
|
dce112_max_clks_by_state,
|
sizeof(dce112_max_clks_by_state));
|
|
dce_clk_mgr_construct(
|
clk_mgr_dce, ctx, regs, clk_shift, clk_mask);
|
|
clk_mgr_dce->base.funcs = &dce112_funcs;
|
|
return &clk_mgr_dce->base;
|
}
|
|
struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx)
|
{
|
struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
|
|
if (clk_mgr_dce == NULL) {
|
BREAK_TO_DEBUGGER();
|
return NULL;
|
}
|
|
memcpy(clk_mgr_dce->max_clks_by_state,
|
dce120_max_clks_by_state,
|
sizeof(dce120_max_clks_by_state));
|
|
dce_clk_mgr_construct(
|
clk_mgr_dce, ctx, NULL, NULL, NULL);
|
|
clk_mgr_dce->dprefclk_khz = 600000;
|
clk_mgr_dce->base.funcs = &dce120_funcs;
|
|
return &clk_mgr_dce->base;
|
}
|
|
struct clk_mgr *dce121_clk_mgr_create(struct dc_context *ctx)
|
{
|
struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce),
|
GFP_KERNEL);
|
|
if (clk_mgr_dce == NULL) {
|
BREAK_TO_DEBUGGER();
|
return NULL;
|
}
|
|
memcpy(clk_mgr_dce->max_clks_by_state, dce120_max_clks_by_state,
|
sizeof(dce120_max_clks_by_state));
|
|
dce_clk_mgr_construct(clk_mgr_dce, ctx, NULL, NULL, NULL);
|
|
clk_mgr_dce->dprefclk_khz = 625000;
|
clk_mgr_dce->base.funcs = &dce120_funcs;
|
|
return &clk_mgr_dce->base;
|
}
|
|
void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr)
|
{
|
struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(*clk_mgr);
|
|
kfree(clk_mgr_dce);
|
*clk_mgr = NULL;
|
}
|
