/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "atom.h"
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#include "include/bios_parser_types.h"
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#include "command_table_helper.h"
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bool dal_bios_parser_init_cmd_tbl_helper(
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const struct command_table_helper **h,
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enum dce_version dce)
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{
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switch (dce) {
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#if defined(CONFIG_DRM_AMD_DC_SI)
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case DCE_VERSION_6_0:
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case DCE_VERSION_6_1:
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case DCE_VERSION_6_4:
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*h = dal_cmd_tbl_helper_dce60_get_table();
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return true;
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#endif
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case DCE_VERSION_8_0:
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case DCE_VERSION_8_1:
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case DCE_VERSION_8_3:
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*h = dal_cmd_tbl_helper_dce80_get_table();
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return true;
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case DCE_VERSION_10_0:
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*h = dal_cmd_tbl_helper_dce110_get_table();
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return true;
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case DCE_VERSION_11_0:
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*h = dal_cmd_tbl_helper_dce110_get_table();
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return true;
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case DCE_VERSION_11_2:
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case DCE_VERSION_11_22:
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*h = dal_cmd_tbl_helper_dce112_get_table();
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return true;
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default:
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/* Unsupported DCE */
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BREAK_TO_DEBUGGER();
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return false;
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}
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}
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/* real implementations */
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bool dal_cmd_table_helper_controller_id_to_atom(
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enum controller_id id,
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uint8_t *atom_id)
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{
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if (atom_id == NULL) {
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BREAK_TO_DEBUGGER();
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return false;
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}
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switch (id) {
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case CONTROLLER_ID_D0:
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*atom_id = ATOM_CRTC1;
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return true;
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case CONTROLLER_ID_D1:
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*atom_id = ATOM_CRTC2;
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return true;
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case CONTROLLER_ID_D2:
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*atom_id = ATOM_CRTC3;
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return true;
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case CONTROLLER_ID_D3:
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*atom_id = ATOM_CRTC4;
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return true;
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case CONTROLLER_ID_D4:
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*atom_id = ATOM_CRTC5;
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return true;
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case CONTROLLER_ID_D5:
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*atom_id = ATOM_CRTC6;
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return true;
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case CONTROLLER_ID_UNDERLAY0:
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*atom_id = ATOM_UNDERLAY_PIPE0;
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return true;
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case CONTROLLER_ID_UNDEFINED:
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*atom_id = ATOM_CRTC_INVALID;
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return true;
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default:
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/* Wrong controller id */
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BREAK_TO_DEBUGGER();
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return false;
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}
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}
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/**
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* translate_transmitter_bp_to_atom
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*
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* @brief
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* Translate the Transmitter to the corresponding ATOM BIOS value
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*
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* @param
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* input transmitter
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* output digitalTransmitter
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* // =00: Digital Transmitter1 ( UNIPHY linkAB )
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* // =01: Digital Transmitter2 ( UNIPHY linkCD )
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* // =02: Digital Transmitter3 ( UNIPHY linkEF )
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*/
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uint8_t dal_cmd_table_helper_transmitter_bp_to_atom(
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enum transmitter t)
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{
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switch (t) {
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case TRANSMITTER_UNIPHY_A:
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case TRANSMITTER_UNIPHY_B:
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case TRANSMITTER_TRAVIS_LCD:
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return 0;
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case TRANSMITTER_UNIPHY_C:
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case TRANSMITTER_UNIPHY_D:
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return 1;
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case TRANSMITTER_UNIPHY_E:
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case TRANSMITTER_UNIPHY_F:
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return 2;
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default:
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/* Invalid Transmitter Type! */
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BREAK_TO_DEBUGGER();
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return 0;
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}
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}
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uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom(
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enum signal_type s,
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bool enable_dp_audio)
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{
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switch (s) {
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case SIGNAL_TYPE_DVI_SINGLE_LINK:
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case SIGNAL_TYPE_DVI_DUAL_LINK:
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return ATOM_ENCODER_MODE_DVI;
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case SIGNAL_TYPE_HDMI_TYPE_A:
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return ATOM_ENCODER_MODE_HDMI;
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case SIGNAL_TYPE_LVDS:
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return ATOM_ENCODER_MODE_LVDS;
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case SIGNAL_TYPE_EDP:
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case SIGNAL_TYPE_DISPLAY_PORT_MST:
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case SIGNAL_TYPE_DISPLAY_PORT:
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case SIGNAL_TYPE_VIRTUAL:
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if (enable_dp_audio)
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return ATOM_ENCODER_MODE_DP_AUDIO;
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else
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return ATOM_ENCODER_MODE_DP;
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case SIGNAL_TYPE_RGB:
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return ATOM_ENCODER_MODE_CRT;
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default:
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return ATOM_ENCODER_MODE_CRT;
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}
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}
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void dal_cmd_table_helper_assign_control_parameter(
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const struct command_table_helper *h,
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struct bp_encoder_control *control,
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DIG_ENCODER_CONTROL_PARAMETERS_V2 *ctrl_param)
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{
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/* there are three transmitter blocks, each one has two links 4-lanes
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* each, A+B, C+D, E+F, Uniphy A, C and E are enumerated as link 0 in
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* each transmitter block B, D and F as link 1, third transmitter block
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* has non splitable links (UniphyE and UniphyF can not be configured
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* separately to drive two different streams)
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*/
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if ((control->transmitter == TRANSMITTER_UNIPHY_B) ||
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(control->transmitter == TRANSMITTER_UNIPHY_D) ||
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(control->transmitter == TRANSMITTER_UNIPHY_F)) {
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/* Bit2: Link Select
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* =0: PHY linkA/C/E
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* =1: PHY linkB/D/F
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*/
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ctrl_param->acConfig.ucLinkSel = 1;
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}
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/* Bit[4:3]: Transmitter Selection
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* =00: Digital Transmitter1 ( UNIPHY linkAB )
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* =01: Digital Transmitter2 ( UNIPHY linkCD )
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* =02: Digital Transmitter3 ( UNIPHY linkEF )
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* =03: Reserved
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*/
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ctrl_param->acConfig.ucTransmitterSel =
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(uint8_t)(h->transmitter_bp_to_atom(control->transmitter));
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/* We need to convert from KHz units into 10KHz units */
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ctrl_param->ucAction = h->encoder_action_to_atom(control->action);
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ctrl_param->usPixelClock = cpu_to_le16((uint16_t)(control->pixel_clock / 10));
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ctrl_param->ucEncoderMode =
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(uint8_t)(h->encoder_mode_bp_to_atom(
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control->signal, control->enable_dp_audio));
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ctrl_param->ucLaneNum = (uint8_t)(control->lanes_number);
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}
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bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src(
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enum clock_source_id id,
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uint32_t *ref_clk_src_id)
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{
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if (ref_clk_src_id == NULL) {
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BREAK_TO_DEBUGGER();
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return false;
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}
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switch (id) {
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case CLOCK_SOURCE_ID_PLL1:
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*ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL;
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return true;
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case CLOCK_SOURCE_ID_PLL2:
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*ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL;
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return true;
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case CLOCK_SOURCE_ID_DCPLL:
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*ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL;
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return true;
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case CLOCK_SOURCE_ID_EXTERNAL:
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*ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK;
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return true;
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case CLOCK_SOURCE_ID_UNDEFINED:
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*ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID;
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return true;
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default:
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/* Unsupported clock source id */
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BREAK_TO_DEBUGGER();
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return false;
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}
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}
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uint8_t dal_cmd_table_helper_encoder_id_to_atom(
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enum encoder_id id)
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{
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switch (id) {
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case ENCODER_ID_INTERNAL_LVDS:
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return ENCODER_OBJECT_ID_INTERNAL_LVDS;
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case ENCODER_ID_INTERNAL_TMDS1:
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return ENCODER_OBJECT_ID_INTERNAL_TMDS1;
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case ENCODER_ID_INTERNAL_TMDS2:
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return ENCODER_OBJECT_ID_INTERNAL_TMDS2;
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case ENCODER_ID_INTERNAL_DAC1:
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return ENCODER_OBJECT_ID_INTERNAL_DAC1;
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case ENCODER_ID_INTERNAL_DAC2:
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return ENCODER_OBJECT_ID_INTERNAL_DAC2;
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case ENCODER_ID_INTERNAL_LVTM1:
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return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
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case ENCODER_ID_INTERNAL_HDMI:
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return ENCODER_OBJECT_ID_HDMI_INTERNAL;
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case ENCODER_ID_EXTERNAL_TRAVIS:
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return ENCODER_OBJECT_ID_TRAVIS;
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case ENCODER_ID_EXTERNAL_NUTMEG:
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return ENCODER_OBJECT_ID_NUTMEG;
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case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
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return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
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case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
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return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
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case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
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return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
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case ENCODER_ID_EXTERNAL_MVPU_FPGA:
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return ENCODER_OBJECT_ID_MVPU_FPGA;
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case ENCODER_ID_INTERNAL_DDI:
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return ENCODER_OBJECT_ID_INTERNAL_DDI;
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case ENCODER_ID_INTERNAL_UNIPHY:
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return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
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case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
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return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA;
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case ENCODER_ID_INTERNAL_UNIPHY1:
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return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1;
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case ENCODER_ID_INTERNAL_UNIPHY2:
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return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2;
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case ENCODER_ID_INTERNAL_UNIPHY3:
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return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
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case ENCODER_ID_INTERNAL_WIRELESS:
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return ENCODER_OBJECT_ID_INTERNAL_VCE;
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case ENCODER_ID_UNKNOWN:
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return ENCODER_OBJECT_ID_NONE;
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default:
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/* Invalid encoder id */
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BREAK_TO_DEBUGGER();
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return ENCODER_OBJECT_ID_NONE;
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}
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}
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