/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_IDS_H__
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#define __AMDGPU_IDS_H__
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#include <linux/types.h>
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#include <linux/mutex.h>
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#include <linux/list.h>
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#include <linux/dma-fence.h>
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#include "amdgpu_sync.h"
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/* maximum number of VMIDs */
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#define AMDGPU_NUM_VMID 16
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struct amdgpu_device;
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struct amdgpu_vm;
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struct amdgpu_ring;
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struct amdgpu_sync;
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struct amdgpu_job;
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struct amdgpu_vmid {
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struct list_head list;
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struct amdgpu_sync active;
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struct dma_fence *last_flush;
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uint64_t owner;
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uint64_t pd_gpu_addr;
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/* last flushed PD/PT update */
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struct dma_fence *flushed_updates;
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uint32_t current_gpu_reset_count;
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uint32_t gds_base;
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uint32_t gds_size;
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uint32_t gws_base;
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uint32_t gws_size;
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uint32_t oa_base;
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uint32_t oa_size;
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unsigned pasid;
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struct dma_fence *pasid_mapping;
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};
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struct amdgpu_vmid_mgr {
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struct mutex lock;
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unsigned num_ids;
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struct list_head ids_lru;
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struct amdgpu_vmid ids[AMDGPU_NUM_VMID];
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atomic_t reserved_vmid_num;
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};
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int amdgpu_pasid_alloc(unsigned int bits);
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void amdgpu_pasid_free(u32 pasid);
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void amdgpu_pasid_free_delayed(struct dma_resv *resv,
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u32 pasid);
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bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
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struct amdgpu_vmid *id);
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int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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unsigned vmhub);
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void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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unsigned vmhub);
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int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
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struct amdgpu_sync *sync, struct dma_fence *fence,
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struct amdgpu_job *job);
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void amdgpu_vmid_reset(struct amdgpu_device *adev, unsigned vmhub,
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unsigned vmid);
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void amdgpu_vmid_reset_all(struct amdgpu_device *adev);
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void amdgpu_vmid_mgr_init(struct amdgpu_device *adev);
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void amdgpu_vmid_mgr_fini(struct amdgpu_device *adev);
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#endif
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