// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2014-2023 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#include <mali_kbase.h>
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#include <mali_kbase_hwaccess_time.h>
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#if MALI_USE_CSF
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#include <asm/arch_timer.h>
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#include <linux/gcd.h>
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#include <csf/mali_kbase_csf_timeout.h>
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#endif
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#include <device/mali_kbase_device.h>
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#include <backend/gpu/mali_kbase_pm_internal.h>
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#include <mali_kbase_config_defaults.h>
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void kbase_backend_get_gpu_time_norequest(struct kbase_device *kbdev,
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u64 *cycle_counter,
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u64 *system_time,
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struct timespec64 *ts)
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{
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u32 hi1, hi2;
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if (cycle_counter)
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*cycle_counter = kbase_backend_get_cycle_cnt(kbdev);
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if (system_time) {
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/* Read hi, lo, hi to ensure a coherent u64 */
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do {
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hi1 = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(TIMESTAMP_HI));
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*system_time = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(TIMESTAMP_LO));
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hi2 = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(TIMESTAMP_HI));
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} while (hi1 != hi2);
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*system_time |= (((u64) hi1) << 32);
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}
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/* Record the CPU's idea of current time */
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if (ts != NULL)
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#if (KERNEL_VERSION(4, 17, 0) > LINUX_VERSION_CODE)
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*ts = ktime_to_timespec64(ktime_get_raw());
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#else
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ktime_get_raw_ts64(ts);
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#endif
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}
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#if !MALI_USE_CSF
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/**
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* timedwait_cycle_count_active() - Timed wait till CYCLE_COUNT_ACTIVE is active
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*
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* @kbdev: Kbase device
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*
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* Return: true if CYCLE_COUNT_ACTIVE is active within the timeout.
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*/
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static bool timedwait_cycle_count_active(struct kbase_device *kbdev)
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{
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#if IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI)
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return true;
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#else
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bool success = false;
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const unsigned int timeout = 100;
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const unsigned long remaining = jiffies + msecs_to_jiffies(timeout);
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while (time_is_after_jiffies(remaining)) {
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if ((kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_STATUS)) &
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GPU_STATUS_CYCLE_COUNT_ACTIVE)) {
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success = true;
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break;
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}
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}
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return success;
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#endif
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}
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#endif
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void kbase_backend_get_gpu_time(struct kbase_device *kbdev, u64 *cycle_counter,
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u64 *system_time, struct timespec64 *ts)
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{
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#if !MALI_USE_CSF
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kbase_pm_request_gpu_cycle_counter(kbdev);
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WARN_ONCE(kbdev->pm.backend.l2_state != KBASE_L2_ON,
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"L2 not powered up");
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WARN_ONCE((!timedwait_cycle_count_active(kbdev)),
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"Timed out on CYCLE_COUNT_ACTIVE");
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#endif
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kbase_backend_get_gpu_time_norequest(kbdev, cycle_counter, system_time,
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ts);
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#if !MALI_USE_CSF
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kbase_pm_release_gpu_cycle_counter(kbdev);
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#endif
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}
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unsigned int kbase_get_timeout_ms(struct kbase_device *kbdev,
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enum kbase_timeout_selector selector)
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{
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/* Timeout calculation:
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* dividing number of cycles by freq in KHz automatically gives value
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* in milliseconds. nr_cycles will have to be multiplied by 1e3 to
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* get result in microseconds, and 1e6 to get result in nanoseconds.
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*/
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u64 timeout, nr_cycles = 0;
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u64 freq_khz;
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/* Only for debug messages, safe default in case it's mis-maintained */
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const char *selector_str = "(unknown)";
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if (!kbdev->lowest_gpu_freq_khz) {
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dev_dbg(kbdev->dev,
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"Lowest frequency uninitialized! Using reference frequency for scaling");
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freq_khz = DEFAULT_REF_TIMEOUT_FREQ_KHZ;
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} else {
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freq_khz = kbdev->lowest_gpu_freq_khz;
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}
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switch (selector) {
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case MMU_AS_INACTIVE_WAIT_TIMEOUT:
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selector_str = "MMU_AS_INACTIVE_WAIT_TIMEOUT";
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nr_cycles = MMU_AS_INACTIVE_WAIT_TIMEOUT_CYCLES;
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break;
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case KBASE_TIMEOUT_SELECTOR_COUNT:
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default:
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#if !MALI_USE_CSF
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WARN(1, "Invalid timeout selector used! Using default value");
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nr_cycles = JM_DEFAULT_TIMEOUT_CYCLES;
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break;
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case JM_DEFAULT_JS_FREE_TIMEOUT:
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selector_str = "JM_DEFAULT_JS_FREE_TIMEOUT";
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nr_cycles = JM_DEFAULT_JS_FREE_TIMEOUT_CYCLES;
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break;
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#else
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/* Use Firmware timeout if invalid selection */
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WARN(1,
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"Invalid timeout selector used! Using CSF Firmware timeout");
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fallthrough;
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case CSF_FIRMWARE_TIMEOUT:
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selector_str = "CSF_FIRMWARE_TIMEOUT";
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/* Any FW timeout cannot be longer than the FW ping interval, after which
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* the firmware_aliveness_monitor will be triggered and may restart
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* the GPU if the FW is unresponsive.
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*/
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nr_cycles = min(CSF_FIRMWARE_PING_TIMEOUT_CYCLES, CSF_FIRMWARE_TIMEOUT_CYCLES);
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if (nr_cycles == CSF_FIRMWARE_PING_TIMEOUT_CYCLES)
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dev_warn(kbdev->dev, "Capping %s to CSF_FIRMWARE_PING_TIMEOUT\n",
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selector_str);
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break;
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case CSF_PM_TIMEOUT:
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selector_str = "CSF_PM_TIMEOUT";
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nr_cycles = CSF_PM_TIMEOUT_CYCLES;
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break;
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case CSF_GPU_RESET_TIMEOUT:
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selector_str = "CSF_GPU_RESET_TIMEOUT";
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nr_cycles = CSF_GPU_RESET_TIMEOUT_CYCLES;
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break;
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case CSF_CSG_SUSPEND_TIMEOUT:
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selector_str = "CSF_CSG_SUSPEND_TIMEOUT";
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nr_cycles = CSF_CSG_SUSPEND_TIMEOUT_CYCLES;
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break;
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case CSF_FIRMWARE_BOOT_TIMEOUT:
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selector_str = "CSF_FIRMWARE_BOOT_TIMEOUT";
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nr_cycles = CSF_FIRMWARE_BOOT_TIMEOUT_CYCLES;
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break;
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case CSF_FIRMWARE_PING_TIMEOUT:
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selector_str = "CSF_FIRMWARE_PING_TIMEOUT";
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nr_cycles = CSF_FIRMWARE_PING_TIMEOUT_CYCLES;
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break;
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case CSF_SCHED_PROTM_PROGRESS_TIMEOUT:
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selector_str = "CSF_SCHED_PROTM_PROGRESS_TIMEOUT";
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nr_cycles = kbase_csf_timeout_get(kbdev);
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break;
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#endif
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}
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timeout = div_u64(nr_cycles, freq_khz);
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if (WARN(timeout > UINT_MAX,
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"Capping excessive timeout %llums for %s at freq %llukHz to UINT_MAX ms",
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(unsigned long long)timeout, selector_str, (unsigned long long)freq_khz))
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timeout = UINT_MAX;
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return (unsigned int)timeout;
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}
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KBASE_EXPORT_TEST_API(kbase_get_timeout_ms);
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u64 kbase_backend_get_cycle_cnt(struct kbase_device *kbdev)
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{
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u32 hi1, hi2, lo;
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/* Read hi, lo, hi to ensure a coherent u64 */
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do {
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hi1 = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(CYCLE_COUNT_HI));
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lo = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(CYCLE_COUNT_LO));
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hi2 = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(CYCLE_COUNT_HI));
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} while (hi1 != hi2);
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return lo | (((u64) hi1) << 32);
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}
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#if MALI_USE_CSF
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u64 __maybe_unused kbase_backend_time_convert_gpu_to_cpu(struct kbase_device *kbdev, u64 gpu_ts)
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{
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if (WARN_ON(!kbdev))
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return 0;
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return div64_u64(gpu_ts * kbdev->backend_time.multiplier, kbdev->backend_time.divisor) +
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kbdev->backend_time.offset;
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}
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/**
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* get_cpu_gpu_time() - Get current CPU and GPU timestamps.
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*
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* @kbdev: Kbase device.
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* @cpu_ts: Output CPU timestamp.
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* @gpu_ts: Output GPU timestamp.
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* @gpu_cycle: Output GPU cycle counts.
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*/
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static void get_cpu_gpu_time(struct kbase_device *kbdev, u64 *cpu_ts, u64 *gpu_ts, u64 *gpu_cycle)
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{
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struct timespec64 ts;
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kbase_backend_get_gpu_time(kbdev, gpu_cycle, gpu_ts, &ts);
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if (cpu_ts)
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*cpu_ts = ts.tv_sec * NSEC_PER_SEC + ts.tv_nsec;
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}
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#endif
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int kbase_backend_time_init(struct kbase_device *kbdev)
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{
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#if MALI_USE_CSF
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u64 cpu_ts = 0;
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u64 gpu_ts = 0;
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u64 freq;
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u64 common_factor;
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get_cpu_gpu_time(kbdev, &cpu_ts, &gpu_ts, NULL);
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freq = arch_timer_get_cntfrq();
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if (!freq) {
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dev_warn(kbdev->dev, "arch_timer_get_rate() is zero!");
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return -EINVAL;
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}
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common_factor = gcd(NSEC_PER_SEC, freq);
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kbdev->backend_time.multiplier = div64_u64(NSEC_PER_SEC, common_factor);
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kbdev->backend_time.divisor = div64_u64(freq, common_factor);
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if (!kbdev->backend_time.divisor) {
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dev_warn(kbdev->dev, "CPU to GPU divisor is zero!");
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return -EINVAL;
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}
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kbdev->backend_time.offset = cpu_ts - div64_u64(gpu_ts * kbdev->backend_time.multiplier,
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kbdev->backend_time.divisor);
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#endif
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return 0;
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}
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