/* SPDX-License-Identifier: GPL-2.0
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*
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* include/asm-sh/cpu-sh2a/cache.h
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*
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* Copyright (C) 2004 Paul Mundt
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*/
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#ifndef __ASM_CPU_SH2A_CACHE_H
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#define __ASM_CPU_SH2A_CACHE_H
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#define L1_CACHE_SHIFT 4
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#define SH_CACHE_VALID 1
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#define SH_CACHE_UPDATED 2
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#define SH_CACHE_COMBINED 4
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#define SH_CACHE_ASSOC 8
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#define SH_CCR 0xfffc1000 /* CCR1 */
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#define SH_CCR2 0xfffc1004
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/*
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* Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
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* listed here are reserved.
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*/
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#define CCR_CACHE_CB 0x0000 /* Hack */
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#define CCR_CACHE_OCE 0x0001
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#define CCR_CACHE_WT 0x0002
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#define CCR_CACHE_OCI 0x0008 /* OCF */
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#define CCR_CACHE_ICE 0x0100
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#define CCR_CACHE_ICI 0x0800 /* ICF */
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#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
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#define CACHE_OC_ADDRESS_ARRAY 0xf0800000
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#define CCR_CACHE_ENABLE (CCR_CACHE_OCE | CCR_CACHE_ICE)
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#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI | CCR_CACHE_ICI)
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#define CCR_ICACHE_INVALIDATE CCR_CACHE_ICI
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#define CCR_OCACHE_INVALIDATE CCR_CACHE_OCI
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#define CACHE_PHYSADDR_MASK 0x1ffffc00
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#endif /* __ASM_CPU_SH2A_CACHE_H */
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