/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_MACH_LOONGSON64_IRQ_H_
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#define __ASM_MACH_LOONGSON64_IRQ_H_
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/* cpu core interrupt numbers */
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#define NR_IRQS_LEGACY 16
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#define NR_MIPS_CPU_IRQS 8
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#define NR_MAX_CHAINED_IRQS 40 /* Chained IRQs means those not directly used by devices */
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#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256)
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#define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
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#include <asm/mach-generic/irq.h>
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#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
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