/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005-2008 Cavium Networks, Inc
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*/
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#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
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#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
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#define CP0_CVMCTL_REG $9, 7
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#define CP0_CVMMEMCTL_REG $11,7
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#define CP0_PRID_REG $15, 0
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#define CP0_DCACHE_ERR_REG $27, 1
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#define CP0_PRID_OCTEON_PASS1 0x000d0000
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#define CP0_PRID_OCTEON_CN30XX 0x000d0200
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.macro kernel_entry_setup
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# Registers set by bootloader:
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# (only 32 bits set by bootloader, all addresses are physical
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# addresses, and need to have the appropriate memory region set
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# by the kernel
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# a0 = argc
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# a1 = argv (kseg0 compat addr)
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# a2 = 1 if init core, zero otherwise
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# a3 = address of boot descriptor block
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.set push
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.set arch=octeon
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# Read the cavium mem control register
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dmfc0 v0, CP0_CVMMEMCTL_REG
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# Clear the lower 6 bits, the CVMSEG size
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dins v0, $0, 0, 6
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ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
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dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
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dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
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# Disable unaligned load/store support but leave HW fixup enabled
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# Needed for octeon specific memcpy
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or v0, v0, 0x5001
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xor v0, v0, 0x1001
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# First clear off CvmCtl[IPPCI] bit and move the performance
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# counters interrupt to IRQ 6
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dli v1, ~(7 << 7)
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and v0, v0, v1
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ori v0, v0, (6 << 7)
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mfc0 v1, CP0_PRID_REG
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and t1, v1, 0xfff8
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xor t1, t1, 0x9000 # 63-P1
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beqz t1, 4f
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and t1, v1, 0xfff8
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xor t1, t1, 0x9008 # 63-P2
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beqz t1, 4f
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and t1, v1, 0xfff8
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xor t1, t1, 0x9100 # 68-P1
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beqz t1, 4f
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and t1, v1, 0xff00
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xor t1, t1, 0x9200 # 66-PX
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bnez t1, 5f # Skip WAR for others.
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and t1, v1, 0x00ff
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slti t1, t1, 2 # 66-P1.2 and later good.
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beqz t1, 5f
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4: # core-16057 work around
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or v0, v0, 0x2000 # Set IPREF bit.
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5: # No core-16057 work around
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# Write the cavium control register
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dmtc0 v0, CP0_CVMCTL_REG
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sync
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# Flush dcache after config change
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cache 9, 0($0)
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# Zero all of CVMSEG to make sure parity is correct
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dli v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
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dsll v0, 7
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beqz v0, 2f
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1: dsubu v0, 8
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sd $0, -32768(v0)
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bnez v0, 1b
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2:
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mfc0 v0, CP0_PRID_REG
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bbit0 v0, 15, 1f
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# OCTEON II or better have bit 15 set. Clear the error bits.
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and t1, v0, 0xff00
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dli v0, 0x9500
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bge t1, v0, 1f # OCTEON III has no DCACHE_ERR_REG COP0
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dli v0, 0x27
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dmtc0 v0, CP0_DCACHE_ERR_REG
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1:
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# Get my core id
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rdhwr v0, $0
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# Jump the master to kernel_entry
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bne a2, zero, octeon_main_processor
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nop
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#ifdef CONFIG_SMP
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#
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# All cores other than the master need to wait here for SMP bootstrap
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# to begin
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#
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octeon_spin_wait_boot:
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#ifdef CONFIG_RELOCATABLE
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PTR_LA t0, octeon_processor_relocated_kernel_entry
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LONG_L t0, (t0)
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beq zero, t0, 1f
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nop
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jr t0
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nop
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1:
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#endif /* CONFIG_RELOCATABLE */
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# This is the variable where the next core to boot is stored
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PTR_LA t0, octeon_processor_boot
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# Get the core id of the next to be booted
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LONG_L t1, (t0)
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# Keep looping if it isn't me
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bne t1, v0, octeon_spin_wait_boot
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nop
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# Get my GP from the global variable
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PTR_LA t0, octeon_processor_gp
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LONG_L gp, (t0)
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# Get my SP from the global variable
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PTR_LA t0, octeon_processor_sp
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LONG_L sp, (t0)
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# Set the SP global variable to zero so the master knows we've started
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LONG_S zero, (t0)
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#ifdef __OCTEON__
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syncw
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syncw
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#else
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sync
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#endif
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# Jump to the normal Linux SMP entry point
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j smp_bootstrap
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nop
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#else /* CONFIG_SMP */
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#
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# Someone tried to boot SMP with a non SMP kernel. All extra cores
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# will halt here.
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#
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octeon_wait_forever:
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wait
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b octeon_wait_forever
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nop
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#endif /* CONFIG_SMP */
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octeon_main_processor:
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.set pop
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.endm
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/*
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* Do SMP slave processor setup necessary before we can safely execute C code.
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*/
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.macro smp_slave_setup
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.endm
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#endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */
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