// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Marvell Armada 388 Reference Design board
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* (RD-88F6820-AP)
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*/
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/dts-v1/;
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#include "armada-388.dtsi"
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/ {
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model = "Marvell Armada 385 Reference Design";
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compatible = "marvell,a385-rd", "marvell,armada388",
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"marvell,armada385","marvell,armada380";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; /* 256 MB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
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internal-regs {
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i2c@11000 {
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status = "okay";
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clock-frequency = <100000>;
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};
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sdhci@d8000 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdhci_pins>;
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broken-cd;
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no-1-8-v;
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wp-inverted;
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bus-width = <8>;
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status = "okay";
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};
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serial@12000 {
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status = "okay";
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};
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ethernet@30000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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ethernet@70000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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mdio@72004 {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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usb3@f0000 {
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status = "okay";
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};
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};
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pcie {
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status = "okay";
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/*
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* One PCIe units is accessible through
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* standard PCIe slot on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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};
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};
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};
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&spi0 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p128", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <108000000>;
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};
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};
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