// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Rockchip Electronics Co., Ltd
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*
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* Author: Wyon Bi <bivvy.bi@rock-chips.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <drm/drm_mipi_dsi.h>
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#include <video_bridge.h>
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#include <asm/unaligned.h>
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#include <linux/math64.h>
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#include "rockchip_display.h"
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#include "rockchip_bridge.h"
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#include "rk618.h"
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/* host registers */
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#define HOSTREG(x) ((x) + 0x1000)
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#define DSI_VERSION HOSTREG(0x0000)
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#define DSI_PWR_UP HOSTREG(0x0004)
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#define SHUTDOWNZ BIT(0)
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#define POWER_UP BIT(0)
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#define RESET 0
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#define DSI_CLKMGR_CFG HOSTREG(0x0008)
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#define TO_CLK_DIVIDSION(x) UPDATE(x, 15, 8)
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#define TX_ESC_CLK_DIVIDSION(x) UPDATE(x, 7, 0)
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#define DSI_DPI_CFG HOSTREG(0x000c)
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#define EN18_LOOSELY BIT(10)
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#define COLORM_ACTIVE_LOW BIT(9)
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#define SHUTD_ACTIVE_LOW BIT(8)
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#define HSYNC_ACTIVE_LOW BIT(7)
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#define VSYNC_ACTIVE_LOW BIT(6)
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#define DATAEN_ACTIVE_LOW BIT(5)
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#define DPI_COLOR_CODING(x) UPDATE(x, 4, 2)
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#define DPI_VID(x) UPDATE(x, 1, 0)
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#define DSI_PCKHDL_CFG HOSTREG(0x0018)
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#define GEN_VID_RX(x) UPDATE(x, 6, 5)
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#define EN_CRC_RX BIT(4)
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#define EN_ECC_RX BIT(3)
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#define EN_BTA BIT(2)
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#define EN_EOTP_RX BIT(1)
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#define EN_EOTP_TX BIT(0)
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#define DSI_VID_MODE_CFG HOSTREG(0x001c)
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#define LPCMDEN BIT(12)
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#define FRAME_BTA_ACK BIT(11)
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#define EN_NULL_PKT BIT(10)
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#define EN_MULTI_PKT BIT(9)
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#define EN_LP_HFP BIT(8)
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#define EN_LP_HBP BIT(7)
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#define EN_LP_VACT BIT(6)
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#define EN_LP_VFP BIT(5)
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#define EN_LP_VBP BIT(4)
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#define EN_LP_VSA BIT(3)
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#define VID_MODE_TYPE(x) UPDATE(x, 2, 1)
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#define EN_VIDEO_MODE BIT(0)
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#define DSI_VID_PKT_CFG HOSTREG(0x0020)
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#define NULL_PKT_SIZE(x) UPDATE(x, 30, 21)
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#define NUM_CHUNKS(x) UPDATE(x, 20, 11)
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#define VID_PKT_SIZE(x) UPDATE(x, 10, 0)
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#define DSI_CMD_MODE_CFG HOSTREG(0x0024)
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#define TEAR_FX_EN BIT(14)
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#define ACK_RQST_EN BIT(13)
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#define DCS_LW_TX BIT(12)
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#define GEN_LW_TX BIT(11)
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#define MAX_RD_PKT_SIZE BIT(10)
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#define DCS_SR_0P_TX BIT(9)
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#define DCS_SW_1P_TX BIT(8)
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#define DCS_SW_0P_TX BIT(7)
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#define GEN_SR_2P_TX BIT(6)
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#define GEN_SR_1P_TX BIT(5)
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#define GEN_SR_0P_TX BIT(4)
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#define GEN_SW_2P_TX BIT(3)
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#define GEN_SW_1P_TX BIT(2)
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#define GEN_SW_0P_TX BIT(1)
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#define EN_CMD_MODE BIT(0)
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#define DSI_TMR_LINE_CFG HOSTREG(0x0028)
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#define HLINE_TIME(x) UPDATE(x, 31, 18)
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#define HBP_TIME(x) UPDATE(x, 17, 9)
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#define HSA_TIME(x) UPDATE(x, 8, 0)
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#define DSI_VTIMING_CFG HOSTREG(0x002c)
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#define V_ACTIVE_LINES(x) UPDATE(x, 26, 16)
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#define VFP_LINES(x) UPDATE(x, 15, 10)
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#define VBP_LINES(x) UPDATE(x, 9, 4)
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#define VSA_LINES(x) UPDATE(x, 3, 0)
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#define DSI_PHY_TMR_CFG HOSTREG(0x0030)
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#define PHY_HS2LP_TIME(x) UPDATE(x, 31, 24)
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#define PHY_LP2HS_TIME(x) UPDATE(x, 23, 16)
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#define MAX_RD_TIME(x) UPDATE(x, 14, 0)
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#define DSI_GEN_HDR HOSTREG(0x0034)
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#define DSI_GEN_PLD_DATA HOSTREG(0x0038)
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#define DSI_GEN_PKT_STATUS HOSTREG(0x003c)
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#define GEN_RD_CMD_BUSY BIT(6)
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#define GEN_PLD_R_FULL BIT(5)
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#define GEN_PLD_R_EMPTY BIT(4)
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#define GEN_PLD_W_FULL BIT(3)
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#define GEN_PLD_W_EMPTY BIT(2)
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#define GEN_CMD_FULL BIT(1)
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#define GEN_CMD_EMPTY BIT(0)
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#define DSI_TO_CNT_CFG HOSTREG(0x0040)
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#define LPRX_TO_CNT(x) UPDATE(x, 31, 16)
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#define HSTX_TO_CNT(x) UPDATE(x, 15, 0)
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#define DSI_INT_ST0 HOSTREG(0x0044)
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#define DSI_INT_ST1 HOSTREG(0x0048)
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#define DSI_INT_MSK0 HOSTREG(0x004c)
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#define DSI_INT_MSK1 HOSTREG(0x0050)
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#define DSI_PHY_RSTZ HOSTREG(0x0054)
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#define PHY_ENABLECLK BIT(2)
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#define DSI_PHY_IF_CFG HOSTREG(0x0058)
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#define PHY_STOP_WAIT_TIME(x) UPDATE(x, 9, 2)
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#define N_LANES(x) UPDATE(x, 1, 0)
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#define DSI_PHY_IF_CTRL HOSTREG(0x005c)
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#define PHY_TX_TRIGGERS(x) UPDATE(x, 8, 5)
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#define PHY_TXEXITULPSLAN BIT(4)
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#define PHY_TXREQULPSLAN BIT(3)
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#define PHY_TXEXITULPSCLK BIT(2)
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#define PHY_RXREQULPSCLK BIT(1)
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#define PHY_TXREQUESCLKHS BIT(0)
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#define DSI_PHY_STATUS HOSTREG(0x0060)
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#define ULPSACTIVENOT3LANE BIT(12)
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#define PHYSTOPSTATE3LANE BIT(11)
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#define ULPSACTIVENOT2LANE BIT(10)
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#define PHYSTOPSTATE2LANE BIT(9)
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#define ULPSACTIVENOT1LANE BIT(8)
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#define PHYSTOPSTATE1LANE BIT(7)
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#define RXULPSESC0LANE BIT(6)
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#define ULPSACTIVENOT0LANE BIT(5)
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#define PHYSTOPSTATE0LANE BIT(4)
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#define PHYULPSACTIVENOTCLK BIT(3)
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#define PHYSTOPSTATECLKLANE BIT(2)
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#define PHYSTOPSTATELANE (PHYSTOPSTATE0LANE | PHYSTOPSTATECLKLANE)
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#define PHYDIRECTION BIT(1)
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#define PHYLOCK BIT(0)
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#define DSI_LP_CMD_TIM HOSTREG(0x0070)
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#define OUTVACT_LPCMD_TIME(x) UPDATE(x, 15, 8)
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#define INVACT_LPCMD_TIME(x) UPDATE(x, 7, 0)
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#define DSI_MAX_REGISTER DSI_LP_CMD_TIM
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/* phy registers */
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#define PHYREG(x) ((x) + 0x0c00)
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#define MIPI_PHY_REG0 PHYREG(0x0000)
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#define LANE_EN_MASK GENMASK(6, 2)
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#define LANE_EN_CK BIT(6)
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#define MIPI_PHY_REG1 PHYREG(0x0004)
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#define REG_DA_PPFC BIT(4)
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#define REG_DA_SYNCRST BIT(2)
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#define REG_DA_LDOPD BIT(1)
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#define REG_DA_PLLPD BIT(0)
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#define MIPI_PHY_REG3 PHYREG(0x000c)
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#define REG_FBDIV_HI_MASK GENMASK(5, 5)
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#define REG_FBDIV_HI(x) UPDATE(x, 5, 5)
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#define REG_PREDIV_MASK GENMASK(4, 0)
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#define REG_PREDIV(x) UPDATE(x, 4, 0)
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#define MIPI_PHY_REG4 PHYREG(0x0010)
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#define REG_FBDIV_LO_MASK GENMASK(7, 0)
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#define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
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#define MIPI_PHY_REG5 PHYREG(0x0014)
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#define MIPI_PHY_REG6 PHYREG(0x0018)
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#define MIPI_PHY_REG7 PHYREG(0x001c)
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#define MIPI_PHY_REG9 PHYREG(0x0024)
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#define MIPI_PHY_REG20 PHYREG(0x0080)
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#define REG_DIG_RSTN BIT(0)
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#define MIPI_PHY_MAX_REGISTER PHYREG(0x0348)
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#define THS_SETTLE_OFFSET 0x00
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#define THS_SETTLE_MASK GENMASK(3, 0)
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#define THS_SETTLE(x) UPDATE(x, 3, 0)
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#define TLPX_OFFSET 0x14
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#define TLPX_MASK GENMASK(5, 0)
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#define TLPX(x) UPDATE(x, 5, 0)
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#define THS_PREPARE_OFFSET 0x18
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#define THS_PREPARE_MASK GENMASK(6, 0)
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#define THS_PREPARE(x) UPDATE(x, 6, 0)
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#define THS_ZERO_OFFSET 0x1c
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#define THS_ZERO_MASK GENMASK(5, 0)
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#define THS_ZERO(x) UPDATE(x, 5, 0)
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#define THS_TRAIL_OFFSET 0x20
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#define THS_TRAIL_MASK GENMASK(6, 0)
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#define THS_TRAIL(x) UPDATE(x, 6, 0)
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#define THS_EXIT_OFFSET 0x24
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#define THS_EXIT_MASK GENMASK(4, 0)
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#define THS_EXIT(x) UPDATE(x, 4, 0)
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#define TCLK_POST_OFFSET 0x28
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#define TCLK_POST_MASK GENMASK(3, 0)
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#define TCLK_POST(x) UPDATE(x, 3, 0)
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#define TWAKUP_HI_OFFSET 0x30
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#define TWAKUP_HI_MASK GENMASK(1, 0)
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#define TWAKUP_HI(x) UPDATE(x, 1, 0)
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#define TWAKUP_LO_OFFSET 0x34
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#define TWAKUP_LO_MASK GENMASK(7, 0)
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#define TWAKUP_LO(x) UPDATE(x, 7, 0)
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#define TCLK_PRE_OFFSET 0x38
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#define TCLK_PRE_MASK GENMASK(3, 0)
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#define TCLK_PRE(x) UPDATE(x, 3, 0)
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#define TTA_GO_OFFSET 0x40
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#define TTA_GO_MASK GENMASK(5, 0)
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#define TTA_GO(x) UPDATE(x, 5, 0)
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#define TTA_SURE_OFFSET 0x44
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#define TTA_SURE_MASK GENMASK(5, 0)
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#define TTA_SURE(x) UPDATE(x, 5, 0)
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#define TTA_WAIT_OFFSET 0x48
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#define TTA_WAIT_MASK GENMASK(5, 0)
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#define TTA_WAIT(x) UPDATE(x, 5, 0)
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#define USEC_PER_SEC 1000000L
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#define USEC_PER_MSEC 1000L
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#define PSEC_PER_NSEC 1000L
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#define PSEC_PER_SEC 1000000000000LL
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struct mipi_dphy {
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u8 prediv;
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u16 fbdiv;
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unsigned int rate;
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};
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struct rk618_dsi {
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struct udevice *dev;
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struct rk618 *parent;
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struct mipi_dphy phy;
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unsigned int channel;
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unsigned int lanes;
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enum mipi_dsi_pixel_format format;
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unsigned long mode_flags;
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struct drm_display_mode mode;
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};
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enum {
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NON_BURST_MODE_SYNC_PULSE,
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NON_BURST_MODE_SYNC_EVENT,
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BURST_MODE,
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};
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enum {
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PIXEL_COLOR_CODING_16BIT_1,
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PIXEL_COLOR_CODING_16BIT_2,
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PIXEL_COLOR_CODING_16BIT_3,
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PIXEL_COLOR_CODING_18BIT_1,
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PIXEL_COLOR_CODING_18BIT_2,
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PIXEL_COLOR_CODING_24BIT,
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};
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#define dsi_read_poll_timeout(dsi, addr, val, cond, sleep_us, timeout_us) \
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({ \
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unsigned long timeout = timer_get_us() + (timeout_us); \
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for (;;) { \
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(val) = dsi_read(dsi, addr); \
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if (cond) \
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break; \
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if ((timeout_us) && time_after(timer_get_us(), timeout)) { \
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(val) = dsi_read(dsi, addr); \
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break; \
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} \
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if (sleep_us) \
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udelay(sleep_us); \
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} \
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(cond) ? 0 : -ETIMEDOUT; \
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})
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static inline int dsi_write(struct rk618_dsi *dsi, u32 reg, u32 val)
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{
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return rk618_i2c_write(dsi->parent, reg, val);
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}
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static inline u32 dsi_read(struct rk618_dsi *dsi, u32 reg)
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{
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u32 val;
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rk618_i2c_read(dsi->parent, reg, &val);
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return val;
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}
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static inline void dsi_update_bits(struct rk618_dsi *dsi,
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u32 reg, u32 mask, u32 val)
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{
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u32 orig, tmp;
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orig = dsi_read(dsi, reg);
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tmp = orig & ~mask;
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tmp |= val & mask;
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dsi_write(dsi, reg, tmp);
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}
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static inline bool is_clk_lane(u32 offset)
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{
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if (offset == 0x100)
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return true;
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return false;
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}
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static void rk618_dsi_set_hs_clk(struct rk618_dsi *dsi)
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{
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const struct drm_display_mode *mode = &dsi->mode;
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struct mipi_dphy *phy = &dsi->phy;
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u32 fout, fref, prediv, fbdiv;
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u32 min_delta = UINT_MAX;
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unsigned int value;
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value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0);
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if (value > 0) {
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fout = value * USEC_PER_SEC;
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} else {
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int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
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unsigned int lanes = dsi->lanes;
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u64 bandwidth;
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bandwidth = (u64)mode->clock * 1000 * bpp;
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do_div(bandwidth, lanes);
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/* take 1 / 0.9, since mbps must big than bandwidth of RGB */
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bandwidth *= 10;
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do_div(bandwidth, 9);
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do_div(bandwidth, USEC_PER_SEC);
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bandwidth *= USEC_PER_SEC;
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fout = bandwidth;
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}
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if (fout > 1000000000UL)
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fout = 1000000000UL;
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fref = clk_get_rate(&dsi->parent->clkin);
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for (prediv = 1; prediv <= 12; prediv++) {
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u64 tmp;
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u32 delta;
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if (fref % prediv)
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continue;
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tmp = (u64)fout * prediv;
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do_div(tmp, fref);
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fbdiv = tmp;
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if (fbdiv < 12 || fbdiv > 511)
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continue;
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if (fbdiv == 15)
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continue;
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tmp = (u64)fbdiv * fref;
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do_div(tmp, prediv);
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delta = abs(fout - tmp);
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if (!delta) {
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phy->rate = tmp;
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phy->prediv = prediv;
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phy->fbdiv = fbdiv;
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break;
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} else if (delta < min_delta) {
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phy->rate = tmp;
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phy->prediv = prediv;
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phy->fbdiv = fbdiv;
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min_delta = delta;
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}
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}
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}
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static void rk618_dsi_phy_power_off(struct rk618_dsi *dsi)
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{
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dsi_update_bits(dsi, MIPI_PHY_REG0, LANE_EN_MASK, 0);
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dsi_update_bits(dsi, MIPI_PHY_REG1, REG_DA_LDOPD | REG_DA_PLLPD,
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REG_DA_LDOPD | REG_DA_PLLPD);
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}
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static void rk618_dsi_phy_power_on(struct rk618_dsi *dsi, u32 txclkesc)
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{
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struct mipi_dphy *phy = &dsi->phy;
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u32 offset, value, index;
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const struct {
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unsigned int rate;
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u8 ths_settle;
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u8 ths_zero;
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u8 ths_trail;
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} timing_table[] = {
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{ 110000000, 0x00, 0x03, 0x0c},
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{ 150000000, 0x01, 0x04, 0x0d},
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{ 200000000, 0x02, 0x04, 0x11},
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{ 250000000, 0x03, 0x05, 0x14},
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{ 300000000, 0x04, 0x06, 0x18},
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{ 400000000, 0x05, 0x07, 0x1d},
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{ 500000000, 0x06, 0x08, 0x23},
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{ 600000000, 0x07, 0x0a, 0x29},
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{ 700000000, 0x08, 0x0b, 0x31},
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{ 800000000, 0x09, 0x0c, 0x34},
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{1000000000, 0x0a, 0x0f, 0x40},
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};
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u32 Ttxbyteclkhs, UI, Ttxddrclkhs, Ttxclkesc;
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u32 Tlpx, Ths_exit, Tclk_post, Tclk_pre, Ths_prepare;
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u32 Tta_go, Tta_sure, Tta_wait;
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Ttxbyteclkhs = div_u64(PSEC_PER_SEC, phy->rate / 8);
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UI = Ttxddrclkhs = div_u64(PSEC_PER_SEC, phy->rate);
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Ttxclkesc = div_u64(PSEC_PER_SEC, txclkesc);
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dsi_update_bits(dsi, MIPI_PHY_REG3, REG_FBDIV_HI_MASK |
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REG_PREDIV_MASK, REG_FBDIV_HI(phy->fbdiv >> 8) |
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REG_PREDIV(phy->prediv));
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dsi_update_bits(dsi, MIPI_PHY_REG4,
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REG_FBDIV_LO_MASK, REG_FBDIV_LO(phy->fbdiv));
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dsi_update_bits(dsi, MIPI_PHY_REG1, REG_DA_LDOPD | REG_DA_PLLPD, 0);
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dsi_update_bits(dsi, MIPI_PHY_REG0, LANE_EN_MASK,
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LANE_EN_CK | GENMASK(dsi->lanes - 1 + 2, 2));
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dsi_update_bits(dsi, MIPI_PHY_REG1, REG_DA_SYNCRST, REG_DA_SYNCRST);
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udelay(1);
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dsi_update_bits(dsi, MIPI_PHY_REG1, REG_DA_SYNCRST, 0);
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dsi_update_bits(dsi, MIPI_PHY_REG20, REG_DIG_RSTN, 0);
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udelay(1);
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dsi_update_bits(dsi, MIPI_PHY_REG20, REG_DIG_RSTN, REG_DIG_RSTN);
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/* XXX */
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dsi_write(dsi, MIPI_PHY_REG6, 0x11);
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dsi_write(dsi, MIPI_PHY_REG7, 0x11);
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dsi_write(dsi, MIPI_PHY_REG9, 0xcc);
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if (phy->rate < 800000000)
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dsi_update_bits(dsi, MIPI_PHY_REG1, REG_DA_PPFC, REG_DA_PPFC);
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else
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dsi_write(dsi, MIPI_PHY_REG5, 0x30);
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for (index = 0; index < ARRAY_SIZE(timing_table); index++)
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if (phy->rate <= timing_table[index].rate)
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break;
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if (index == ARRAY_SIZE(timing_table))
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--index;
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for (offset = 0x100; offset <= 0x300; offset += 0x80) {
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dsi_update_bits(dsi, PHYREG(offset + THS_SETTLE_OFFSET),
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THS_SETTLE_MASK,
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THS_SETTLE(timing_table[index].ths_settle));
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/*
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* The value of counter for HS Tlpx Time
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* Tlpx = Tpin_txbyteclkhs * value
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*/
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Tlpx = 60 * PSEC_PER_NSEC;
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value = DIV_ROUND_UP(Tlpx, Ttxbyteclkhs);
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Tlpx = Ttxbyteclkhs * value;
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dsi_update_bits(dsi, PHYREG(offset + TLPX_OFFSET),
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TLPX_MASK, TLPX(value));
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/*
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* The value of counter for HS Ths-prepare
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* For clock lane, Ths-prepare(38ns~95ns)
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* For data lane, Ths-prepare(40ns+4UI~85ns+6UI)
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* Ths-prepare = Ttxddrclkhs * value
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*/
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if (is_clk_lane(offset))
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Ths_prepare = 65 * PSEC_PER_NSEC;
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else
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Ths_prepare = 65 * PSEC_PER_NSEC + 4 * UI;
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value = DIV_ROUND_UP(Ths_prepare, Ttxddrclkhs);
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dsi_update_bits(dsi, PHYREG(offset + THS_PREPARE_OFFSET),
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THS_PREPARE_MASK, THS_PREPARE(value));
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dsi_update_bits(dsi, PHYREG(offset + THS_ZERO_OFFSET),
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THS_ZERO_MASK,
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THS_ZERO(timing_table[index].ths_zero));
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dsi_update_bits(dsi, PHYREG(offset + THS_TRAIL_OFFSET),
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THS_TRAIL_MASK,
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THS_TRAIL(timing_table[index].ths_trail));
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/*
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* The value of counter for HS Ths-exit
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* Ths-exit = Tpin_txbyteclkhs * value
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*/
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Ths_exit = 120 * PSEC_PER_NSEC;
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value = DIV_ROUND_UP(Ths_exit, Ttxbyteclkhs);
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dsi_update_bits(dsi, PHYREG(offset + THS_EXIT_OFFSET),
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THS_EXIT_MASK, THS_EXIT(value));
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/*
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* The value of counter for HS Tclk-post
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* Tclk-post = Ttxbyteclkhs * value
|
*/
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Tclk_post = 70 * PSEC_PER_NSEC + 52 * UI;
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value = DIV_ROUND_UP(Tclk_post, Ttxbyteclkhs);
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dsi_update_bits(dsi, PHYREG(offset + TCLK_POST_OFFSET),
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TCLK_POST_MASK, TCLK_POST(value));
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/*
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* The value of counter for HS Twakup
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* Twakup for ulpm,
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* Twakup = Tpin_sys_clk * value
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*/
|
dsi_update_bits(dsi, PHYREG(offset + TWAKUP_HI_OFFSET),
|
TWAKUP_HI_MASK, TWAKUP_HI(0x3));
|
dsi_update_bits(dsi, PHYREG(offset + TWAKUP_LO_OFFSET),
|
TWAKUP_LO_MASK, TWAKUP_LO(0xff));
|
|
/*
|
* The value of counter for HS Tclk-pre
|
* Tclk-pre for clock lane
|
* Tclk-pre = Tpin_txbyteclkhs * value
|
*/
|
Tclk_pre = 8 * UI;
|
value = DIV_ROUND_UP(Tclk_pre, Ttxbyteclkhs);
|
dsi_update_bits(dsi, PHYREG(offset + TCLK_PRE_OFFSET),
|
TCLK_PRE_MASK, TCLK_PRE(value));
|
|
/*
|
* The value of counter for HS Tta-go
|
* Tta-go for turnaround
|
* Tta-go = Ttxclkesc * value
|
*/
|
Tta_go = 4 * Tlpx;
|
value = DIV_ROUND_UP(Tta_go, Ttxclkesc);
|
dsi_update_bits(dsi, PHYREG(offset + TTA_GO_OFFSET),
|
TTA_GO_MASK, TTA_GO(value));
|
|
/*
|
* The value of counter for HS Tta-sure
|
* Tta-sure for turnaround
|
* Tta-sure = Ttxclkesc * value
|
*/
|
Tta_sure = 2 * Tlpx;
|
value = DIV_ROUND_UP(Tta_sure, Ttxclkesc);
|
dsi_update_bits(dsi, PHYREG(offset + TTA_SURE_OFFSET),
|
TTA_SURE_MASK, TTA_SURE(value));
|
|
/*
|
* The value of counter for HS Tta-wait
|
* Tta-wait for turnaround
|
* Interval from receiving ppi turnaround request to
|
* sending esc request.
|
* Tta-wait = Ttxclkesc * value
|
*/
|
Tta_wait = 5 * Tlpx;
|
value = DIV_ROUND_UP(Tta_wait, Ttxclkesc);
|
dsi_update_bits(dsi, PHYREG(offset + TTA_WAIT_OFFSET),
|
TTA_WAIT_MASK, TTA_WAIT(value));
|
}
|
}
|
|
static int rk618_dsi_pre_enable(struct rk618_dsi *dsi)
|
{
|
struct drm_display_mode *mode = &dsi->mode;
|
u32 esc_clk_div, txclkesc;
|
u32 lanebyteclk, dpipclk;
|
u32 hsw, hbp, vsw, vfp, vbp;
|
u32 hsa_time, hbp_time, hline_time;
|
u32 value;
|
int ret;
|
|
rk618_dsi_set_hs_clk(dsi);
|
|
dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, RESET);
|
|
/* Configuration of the internal clock dividers */
|
esc_clk_div = DIV_ROUND_UP(dsi->phy.rate >> 3, 20000000);
|
txclkesc = dsi->phy.rate >> 3 / esc_clk_div;
|
value = TO_CLK_DIVIDSION(10) | TX_ESC_CLK_DIVIDSION(esc_clk_div);
|
dsi_write(dsi, DSI_CLKMGR_CFG, value);
|
|
/* The DPI interface configuration */
|
value = DPI_VID(dsi->channel);
|
|
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
|
value |= VSYNC_ACTIVE_LOW;
|
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
|
value |= HSYNC_ACTIVE_LOW;
|
|
switch (dsi->format) {
|
case MIPI_DSI_FMT_RGB666:
|
value |= DPI_COLOR_CODING(PIXEL_COLOR_CODING_18BIT_2);
|
break;
|
case MIPI_DSI_FMT_RGB666_PACKED:
|
value |= DPI_COLOR_CODING(PIXEL_COLOR_CODING_18BIT_1);
|
value |= EN18_LOOSELY;
|
break;
|
case MIPI_DSI_FMT_RGB565:
|
value |= DPI_COLOR_CODING(PIXEL_COLOR_CODING_16BIT_1);
|
break;
|
case MIPI_DSI_FMT_RGB888:
|
default:
|
value |= DPI_COLOR_CODING(PIXEL_COLOR_CODING_24BIT);
|
break;
|
}
|
|
dsi_write(dsi, DSI_DPI_CFG, value);
|
|
/* Packet handler configuration */
|
value = GEN_VID_RX(dsi->channel) | EN_CRC_RX | EN_ECC_RX | EN_BTA;
|
|
if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
|
value |= EN_EOTP_TX;
|
|
dsi_write(dsi, DSI_PCKHDL_CFG, value);
|
|
/* Video mode configuration */
|
value = EN_LP_VACT | EN_LP_VBP | EN_LP_VFP | EN_LP_VSA;
|
|
if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
|
value |= EN_LP_HFP;
|
|
if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
|
value |= EN_LP_HBP;
|
|
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
|
value |= VID_MODE_TYPE(BURST_MODE);
|
else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
|
value |= VID_MODE_TYPE(NON_BURST_MODE_SYNC_PULSE);
|
else
|
value |= VID_MODE_TYPE(NON_BURST_MODE_SYNC_EVENT);
|
|
dsi_write(dsi, DSI_VID_MODE_CFG, value);
|
|
/* Video packet configuration */
|
dsi_write(dsi, DSI_VID_PKT_CFG, VID_PKT_SIZE(mode->hdisplay));
|
|
/* Timeout timers configuration */
|
dsi_write(dsi, DSI_TO_CNT_CFG, LPRX_TO_CNT(1000) | HSTX_TO_CNT(1000));
|
|
hsw = mode->hsync_end - mode->hsync_start;
|
hbp = mode->htotal - mode->hsync_end;
|
vsw = mode->vsync_end - mode->vsync_start;
|
vfp = mode->vsync_start - mode->vdisplay;
|
vbp = mode->vtotal - mode->vsync_end;
|
|
/* Line timing configuration */
|
lanebyteclk = (dsi->phy.rate >> 3) / USEC_PER_SEC;
|
dpipclk = mode->clock / USEC_PER_MSEC;
|
hline_time = DIV_ROUND_UP(mode->htotal * lanebyteclk, dpipclk);
|
hbp_time = DIV_ROUND_UP(hbp * lanebyteclk, dpipclk);
|
hsa_time = DIV_ROUND_UP(hsw * lanebyteclk, dpipclk);
|
dsi_write(dsi, DSI_TMR_LINE_CFG, HLINE_TIME(hline_time) |
|
HBP_TIME(hbp_time) | HSA_TIME(hsa_time));
|
|
/* Vertical timing configuration */
|
dsi_write(dsi, DSI_VTIMING_CFG,
|
V_ACTIVE_LINES(mode->vdisplay) | VFP_LINES(vfp) |
|
VBP_LINES(vbp) | VSA_LINES(vsw));
|
|
/* D-PHY interface configuration */
|
value = N_LANES(dsi->lanes - 1) | PHY_STOP_WAIT_TIME(0x20);
|
dsi_write(dsi, DSI_PHY_IF_CFG, value);
|
|
/* D-PHY timing configuration */
|
value = PHY_HS2LP_TIME(20) | PHY_LP2HS_TIME(16) | MAX_RD_TIME(10000);
|
dsi_write(dsi, DSI_PHY_TMR_CFG, value);
|
|
/* enables the D-PHY Clock Lane Module */
|
dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK);
|
|
dsi_update_bits(dsi, DSI_VID_MODE_CFG, EN_VIDEO_MODE, 0);
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, EN_CMD_MODE, EN_CMD_MODE);
|
|
rk618_dsi_phy_power_on(dsi, txclkesc);
|
|
/* wait for the PHY to acquire lock */
|
ret = dsi_read_poll_timeout(dsi, DSI_PHY_STATUS,
|
value, value & PHYLOCK, 50, 1000);
|
if (ret) {
|
dev_err(dsi->dev, "PHY is not locked\n");
|
return ret;
|
}
|
|
/* wait for the lane go to the stop state */
|
ret = dsi_read_poll_timeout(dsi, DSI_PHY_STATUS,
|
value, value & PHYSTOPSTATELANE, 50, 1000);
|
if (ret) {
|
dev_err(dsi->dev, "lane module is not in stop state\n");
|
return ret;
|
}
|
|
dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, POWER_UP);
|
|
return 0;
|
}
|
|
static void rk618_dsi_enable(struct rk618_dsi *dsi)
|
{
|
/* controls the D-PHY PPI txrequestclkhs signal */
|
dsi_update_bits(dsi, DSI_PHY_IF_CTRL,
|
PHY_TXREQUESCLKHS, PHY_TXREQUESCLKHS);
|
|
/* enables the DPI Video mode transmission */
|
dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, RESET);
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, EN_CMD_MODE, 0);
|
dsi_update_bits(dsi, DSI_VID_MODE_CFG, EN_VIDEO_MODE, EN_VIDEO_MODE);
|
dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, POWER_UP);
|
|
printf("final DSI-Link bandwidth: %lu x %d Mbps\n",
|
dsi->phy.rate / USEC_PER_SEC, dsi->lanes);
|
}
|
|
static void rk618_dsi_disable(struct rk618_dsi *dsi)
|
{
|
/* enables the Command mode protocol for transmissions */
|
dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, RESET);
|
dsi_update_bits(dsi, DSI_PHY_IF_CTRL, PHY_TXREQUESCLKHS, 0);
|
dsi_update_bits(dsi, DSI_VID_MODE_CFG, EN_VIDEO_MODE, 0);
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, EN_CMD_MODE, EN_CMD_MODE);
|
dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, POWER_UP);
|
}
|
|
static void rk618_dsi_post_disable(struct rk618_dsi *dsi)
|
{
|
dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, RESET);
|
dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);
|
|
rk618_dsi_phy_power_off(dsi);
|
}
|
|
static void rk618_dsi_bridge_pre_enable(struct rockchip_bridge *bridge)
|
{
|
struct rk618_dsi *dsi = dev_get_priv(bridge->dev);
|
|
rk618_dsi_pre_enable(dsi);
|
}
|
|
static void rk618_dsi_bridge_enable(struct rockchip_bridge *bridge)
|
{
|
struct rk618_dsi *dsi = dev_get_priv(bridge->dev);
|
|
rk618_dsi_enable(dsi);
|
}
|
|
static void rk618_dsi_bridge_post_disable(struct rockchip_bridge *bridge)
|
{
|
struct rk618_dsi *dsi = dev_get_priv(bridge->dev);
|
|
rk618_dsi_post_disable(dsi);
|
}
|
|
static void rk618_dsi_bridge_disable(struct rockchip_bridge *bridge)
|
{
|
struct rk618_dsi *dsi = dev_get_priv(bridge->dev);
|
|
rk618_dsi_disable(dsi);
|
}
|
|
static void rk618_dsi_bridge_mode_set(struct rockchip_bridge *bridge,
|
const struct drm_display_mode *mode)
|
{
|
struct rk618_dsi *dsi = dev_get_priv(bridge->dev);
|
|
memcpy(&dsi->mode, mode, sizeof(*mode));
|
}
|
|
static const struct rockchip_bridge_funcs rk618_dsi_bridge_funcs = {
|
.enable = rk618_dsi_bridge_enable,
|
.disable = rk618_dsi_bridge_disable,
|
.pre_enable = rk618_dsi_bridge_pre_enable,
|
.post_disable = rk618_dsi_bridge_post_disable,
|
.mode_set = rk618_dsi_bridge_mode_set,
|
};
|
|
static ssize_t rk618_dsi_transfer(struct rk618_dsi *dsi,
|
const struct mipi_dsi_msg *msg)
|
{
|
struct mipi_dsi_packet packet;
|
u32 value, mask;
|
int ret;
|
|
if (msg->flags & MIPI_DSI_MSG_USE_LPM)
|
dsi_update_bits(dsi, DSI_PHY_IF_CTRL, PHY_TXREQUESCLKHS, 0);
|
else
|
dsi_update_bits(dsi, DSI_PHY_IF_CTRL,
|
PHY_TXREQUESCLKHS, PHY_TXREQUESCLKHS);
|
|
switch (msg->type) {
|
case MIPI_DSI_DCS_SHORT_WRITE:
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX,
|
msg->flags & MIPI_DSI_MSG_USE_LPM ?
|
DCS_SW_0P_TX : 0);
|
break;
|
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX,
|
msg->flags & MIPI_DSI_MSG_USE_LPM ?
|
DCS_SW_1P_TX : 0);
|
break;
|
case MIPI_DSI_DCS_LONG_WRITE:
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX,
|
msg->flags & MIPI_DSI_MSG_USE_LPM ?
|
DCS_LW_TX : 0);
|
break;
|
case MIPI_DSI_DCS_READ:
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX,
|
msg->flags & MIPI_DSI_MSG_USE_LPM ?
|
DCS_SR_0P_TX : 0);
|
break;
|
case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG,
|
MAX_RD_PKT_SIZE,
|
msg->flags & MIPI_DSI_MSG_USE_LPM ?
|
MAX_RD_PKT_SIZE : 0);
|
break;
|
case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX,
|
msg->flags & MIPI_DSI_MSG_USE_LPM ?
|
GEN_SW_0P_TX : 0);
|
break;
|
case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX,
|
msg->flags & MIPI_DSI_MSG_USE_LPM ?
|
GEN_SW_1P_TX : 0);
|
break;
|
case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX,
|
msg->flags & MIPI_DSI_MSG_USE_LPM ?
|
GEN_SW_2P_TX : 0);
|
break;
|
case MIPI_DSI_GENERIC_LONG_WRITE:
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_LW_TX,
|
msg->flags & MIPI_DSI_MSG_USE_LPM ?
|
GEN_LW_TX : 0);
|
break;
|
case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX,
|
msg->flags & MIPI_DSI_MSG_USE_LPM ?
|
GEN_SR_0P_TX : 0);
|
break;
|
case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX,
|
msg->flags & MIPI_DSI_MSG_USE_LPM ?
|
GEN_SR_1P_TX : 0);
|
break;
|
case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
|
dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX,
|
msg->flags & MIPI_DSI_MSG_USE_LPM ?
|
GEN_SR_2P_TX : 0);
|
break;
|
default:
|
return -EINVAL;
|
}
|
|
/* create a packet to the DSI protocol */
|
ret = mipi_dsi_create_packet(&packet, msg);
|
if (ret) {
|
dev_err(dsi->dev, "failed to create packet: %d\n", ret);
|
return ret;
|
}
|
|
/* Send payload */
|
while (packet.payload_length >= 4) {
|
mask = GEN_PLD_W_FULL;
|
ret = dsi_read_poll_timeout(dsi, DSI_GEN_PKT_STATUS,
|
value, !(value & mask), 50, 1000);
|
if (ret) {
|
dev_err(dsi->dev, "Write payload FIFO is full\n");
|
return ret;
|
}
|
|
value = get_unaligned_le32(packet.payload);
|
dsi_write(dsi, DSI_GEN_PLD_DATA, value);
|
packet.payload += 4;
|
packet.payload_length -= 4;
|
}
|
|
value = 0;
|
switch (packet.payload_length) {
|
case 3:
|
value |= packet.payload[2] << 16;
|
/* Fall through */
|
case 2:
|
value |= packet.payload[1] << 8;
|
/* Fall through */
|
case 1:
|
value |= packet.payload[0];
|
dsi_write(dsi, DSI_GEN_PLD_DATA, value);
|
break;
|
}
|
|
mask = GEN_CMD_FULL;
|
ret = dsi_read_poll_timeout(dsi, DSI_GEN_PKT_STATUS,
|
value, !(value & mask), 50, 1000);
|
if (ret) {
|
dev_err(dsi->dev, "Command FIFO is full\n");
|
return ret;
|
}
|
|
/* Send packet header */
|
value = get_unaligned_le32(packet.header);
|
dsi_write(dsi, DSI_GEN_HDR, value);
|
|
mask = GEN_PLD_W_EMPTY | GEN_CMD_EMPTY;
|
ret = dsi_read_poll_timeout(dsi, DSI_GEN_PKT_STATUS,
|
value, (value & mask) == mask, 50, 1000);
|
if (ret) {
|
dev_err(dsi->dev, "Write payload FIFO is not empty\n");
|
return ret;
|
}
|
|
if (msg->rx_len) {
|
u8 *payload = msg->rx_buf;
|
u16 length;
|
|
mask = GEN_RD_CMD_BUSY;
|
ret = dsi_read_poll_timeout(dsi, DSI_GEN_PKT_STATUS,
|
value, !(value & mask), 50, 1000);
|
if (ret) {
|
dev_err(dsi->dev,
|
"entire response is not stored in the FIFO\n");
|
return ret;
|
}
|
|
/* Receive payload */
|
for (length = msg->rx_len; length; length -= 4) {
|
mask = GEN_PLD_R_EMPTY;
|
ret = dsi_read_poll_timeout(dsi, DSI_GEN_PKT_STATUS,
|
value, !(value & mask),
|
50, 1000);
|
if (ret) {
|
dev_err(dsi->dev,
|
"Read payload FIFO is empty\n");
|
return ret;
|
}
|
|
value = dsi_read(dsi, DSI_GEN_PLD_DATA);
|
|
switch (length) {
|
case 3:
|
payload[2] = (value >> 16) & 0xff;
|
/* Fall through */
|
case 2:
|
payload[1] = (value >> 8) & 0xff;
|
/* Fall through */
|
case 1:
|
payload[0] = value & 0xff;
|
return length;
|
}
|
|
payload[0] = (value >> 0) & 0xff;
|
payload[1] = (value >> 8) & 0xff;
|
payload[2] = (value >> 16) & 0xff;
|
payload[3] = (value >> 24) & 0xff;
|
payload += 4;
|
}
|
}
|
|
return packet.payload_length;
|
}
|
|
static int rk618_dsi_probe(struct udevice *dev)
|
{
|
struct rk618_dsi *dsi = dev_get_priv(dev);
|
struct rockchip_bridge *bridge =
|
(struct rockchip_bridge *)dev_get_driver_data(dev);
|
int ret;
|
|
dsi->dev = dev;
|
dsi->parent = dev_get_priv(dev->parent);
|
|
ret = device_probe(dev->parent);
|
if (ret)
|
return ret;
|
|
bridge->dev = dev;
|
|
/* Mask all interrupts */
|
dsi_write(dsi, DSI_INT_MSK0, 0xffffffff);
|
dsi_write(dsi, DSI_INT_MSK1, 0xffffffff);
|
|
return 0;
|
}
|
|
static struct rockchip_bridge rk618_dsi_driver_data = {
|
.funcs = &rk618_dsi_bridge_funcs,
|
};
|
|
static const struct udevice_id rk618_dsi_ids[] = {
|
{
|
.compatible = "rockchip,rk618-dsi",
|
.data = (ulong)&rk618_dsi_driver_data,
|
},
|
{}
|
};
|
|
static ssize_t rk618_dsi_host_transfer(struct mipi_dsi_host *host,
|
const struct mipi_dsi_msg *msg)
|
{
|
struct rk618_dsi *dsi = dev_get_priv(host->dev);
|
|
return rk618_dsi_transfer(dsi, msg);
|
}
|
|
static int rk618_dsi_host_attach(struct mipi_dsi_host *host,
|
struct mipi_dsi_device *device)
|
{
|
struct rk618_dsi *dsi = dev_get_priv(host->dev);
|
|
if (device->lanes < 1 || device->lanes > 4)
|
return -EINVAL;
|
|
dsi->lanes = device->lanes;
|
dsi->channel = device->channel;
|
dsi->format = device->format;
|
dsi->mode_flags = device->mode_flags;
|
|
return 0;
|
}
|
|
static const struct mipi_dsi_host_ops rk618_dsi_host_ops = {
|
.attach = rk618_dsi_host_attach,
|
.transfer = rk618_dsi_host_transfer,
|
};
|
|
static int rk618_dsi_bind(struct udevice *dev)
|
{
|
struct mipi_dsi_host *host = dev_get_platdata(dev);
|
|
host->dev = dev;
|
host->ops = &rk618_dsi_host_ops;
|
|
return dm_scan_fdt_dev(dev);
|
}
|
|
static int rk618_dsi_child_post_bind(struct udevice *dev)
|
{
|
struct mipi_dsi_host *host = dev_get_platdata(dev->parent);
|
struct mipi_dsi_device *device = dev_get_parent_platdata(dev);
|
char name[20];
|
|
sprintf(name, "%s.%d", host->dev->name, device->channel);
|
device_set_name(dev, name);
|
|
device->dev = dev;
|
device->host = host;
|
device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4);
|
device->format = dev_read_u32_default(dev, "dsi,format",
|
MIPI_DSI_FMT_RGB888);
|
device->mode_flags = dev_read_u32_default(dev, "dsi,flags",
|
MIPI_DSI_MODE_VIDEO |
|
MIPI_DSI_MODE_VIDEO_BURST |
|
MIPI_DSI_MODE_VIDEO_HBP |
|
MIPI_DSI_MODE_LPM |
|
MIPI_DSI_MODE_EOT_PACKET);
|
device->channel = dev_read_u32_default(dev, "reg", 0);
|
|
return 0;
|
}
|
|
static int rk618_dsi_child_pre_probe(struct udevice *dev)
|
{
|
struct mipi_dsi_device *device = dev_get_parent_platdata(dev);
|
int ret;
|
|
ret = mipi_dsi_attach(device);
|
if (ret) {
|
dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
|
return ret;
|
}
|
|
return 0;
|
}
|
|
U_BOOT_DRIVER(rk618_dsi) = {
|
.name = "rk618_dsi",
|
.id = UCLASS_VIDEO_BRIDGE,
|
.of_match = rk618_dsi_ids,
|
.probe = rk618_dsi_probe,
|
.bind = rk618_dsi_bind,
|
.priv_auto_alloc_size = sizeof(struct rk618_dsi),
|
.per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device),
|
.platdata_auto_alloc_size = sizeof(struct mipi_dsi_host),
|
.child_post_bind = rk618_dsi_child_post_bind,
|
.child_pre_probe = rk618_dsi_child_pre_probe,
|
};
|
