/*
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* (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <errno.h>
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#include <malloc.h>
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#include <asm/unaligned.h>
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#include <asm/io.h>
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#include <linux/list.h>
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#include <div64.h>
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#include <dm/device.h>
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#include <dm/read.h>
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#include <dm/uclass.h>
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#include <dm/uclass-id.h>
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#include "rockchip_phy.h"
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#define NSEC_PER_USEC 1000L
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#define USEC_PER_SEC 1000000L
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#define NSEC_PER_SEC 1000000000L
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#define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l)))
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/* Innosilicon MIPI D-PHY registers */
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#define INNO_PHY_LANE_CTRL 0x0000
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#define MIPI_BGPD BIT(7)
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#define CLK_LANE_EN_MASK BIT(6)
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#define DATA_LANE_3_EN_MASK BIT(5)
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#define DATA_LANE_2_EN_MASK BIT(4)
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#define DATA_LANE_1_EN_MASK BIT(3)
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#define DATA_LANE_0_EN_MASK BIT(2)
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#define CLK_LANE_EN BIT(6)
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#define DATA_LANE_3_EN BIT(5)
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#define DATA_LANE_2_EN BIT(4)
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#define DATA_LANE_1_EN BIT(3)
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#define DATA_LANE_0_EN BIT(2)
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#define PWROK_BP BIT(1)
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#define PWROK BIT(0)
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#define INNO_PHY_POWER_CTRL 0x0004
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#define ANALOG_RESET_MASK BIT(2)
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#define ANALOG_RESET BIT(2)
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#define ANALOG_NORMAL 0
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#define LDO_POWER_MASK BIT(1)
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#define LDO_POWER_DOWN BIT(1)
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#define LDO_POWER_ON 0
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#define PLL_POWER_MASK BIT(0)
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#define PLL_POWER_DOWN BIT(0)
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#define PLL_POWER_ON 0
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#define INNO_PHY_PLL_CTRL_0 0x000c
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#define FBDIV_HI_MASK BIT(5)
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#define FBDIV_HI(x) UPDATE(x, 5, 5)
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#define PREDIV_MASK GENMASK(4, 0)
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#define PREDIV(x) UPDATE(x, 4, 0)
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#define INNO_PHY_PLL_CTRL_1 0x0010
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#define FBDIV_LO_MASK GENMASK(7, 0)
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#define FBDIV_LO(x) UPDATE(x, 7, 0)
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#define ANALOG_REG_08 0x0020
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#define PRE_EMPHASIS_ENABLE_MASK BIT(7)
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#define PRE_EMPHASIS_ENABLE BIT(7)
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#define PRE_EMPHASIS_DISABLE 0
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#define PLL_POST_DIV_ENABLE_MASK BIT(5)
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#define PLL_POST_DIV_ENABLE BIT(5)
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#define PLL_POST_DIV_DISABLE 0
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#define DATA_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
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#define DATA_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
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#define ANALOG_REG_0B 0x002c
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#define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
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#define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
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#define VOD_MIN_RANGE 0x1
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#define VOD_MID_RANGE 0x3
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#define VOD_BIG_RANGE 0x7
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#define VOD_MAX_RANGE 0xf
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#define INNO_PHY_DIG_CTRL 0x0080
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#define DIGITAL_RESET_MASK BIT(0)
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#define DIGITAL_NORMAL BIT(0)
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#define DIGITAL_RESET 0
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#define INNO_PHY_LVDS_CTRL 0x03ac
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#define LVDS_BGPD BIT(0)
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#define INNO_CLOCK_LANE_REG_BASE 0x0100
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#define INNO_DATA_LANE_0_REG_BASE 0x0180
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#define INNO_DATA_LANE_1_REG_BASE 0x0200
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#define INNO_DATA_LANE_2_REG_BASE 0x0280
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#define INNO_DATA_LANE_3_REG_BASE 0x0300
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#define T_LPX_OFFSET 0x0014
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#define T_HS_PREPARE_OFFSET 0x0018
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#define T_HS_ZERO_OFFSET 0x001c
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#define T_HS_TRAIL_OFFSET 0x0020
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#define T_HS_EXIT_OFFSET 0x0024
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#define T_CLK_POST_OFFSET 0x0028
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#define T_WAKUP_H_OFFSET 0x0030
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#define T_WAKUP_L_OFFSET 0x0034
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#define T_CLK_PRE_OFFSET 0x0038
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#define T_TA_GO_OFFSET 0x0040
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#define T_TA_SURE_OFFSET 0x0044
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#define T_TA_WAIT_OFFSET 0x0048
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#define T_LPX_MASK GENMASK(5, 0)
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#define T_LPX(x) UPDATE(x, 5, 0)
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#define T_HS_PREPARE_MASK GENMASK(6, 0)
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#define T_HS_PREPARE(x) UPDATE(x, 6, 0)
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#define T_HS_ZERO_MASK GENMASK(5, 0)
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#define T_HS_ZERO(x) UPDATE(x, 5, 0)
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#define T_HS_TRAIL_MASK GENMASK(6, 0)
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#define T_HS_TRAIL(x) UPDATE(x, 6, 0)
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#define T_HS_EXIT_MASK GENMASK(4, 0)
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#define T_HS_EXIT(x) UPDATE(x, 4, 0)
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#define T_CLK_POST_MASK GENMASK(3, 0)
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#define T_CLK_POST(x) UPDATE(x, 3, 0)
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#define T_WAKUP_H_MASK GENMASK(1, 0)
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#define T_WAKUP_H(x) UPDATE(x, 1, 0)
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#define T_WAKUP_L_MASK GENMASK(7, 0)
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#define T_WAKUP_L(x) UPDATE(x, 7, 0)
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#define T_CLK_PRE_MASK GENMASK(3, 0)
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#define T_CLK_PRE(x) UPDATE(x, 3, 0)
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#define T_TA_GO_MASK GENMASK(5, 0)
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#define T_TA_GO(x) UPDATE(x, 5, 0)
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#define T_TA_SURE_MASK GENMASK(5, 0)
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#define T_TA_SURE(x) UPDATE(x, 5, 0)
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#define T_TA_WAIT_MASK GENMASK(5, 0)
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#define T_TA_WAIT(x) UPDATE(x, 5, 0)
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enum soc_type {
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RV1108_MIPI_DPHY,
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RK1808_MIPI_DPHY,
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};
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enum lane_type {
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CLOCK_LANE,
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DATA_LANE_0,
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DATA_LANE_1,
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DATA_LANE_2,
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DATA_LANE_3,
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};
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struct mipi_dphy_timing {
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unsigned int clkmiss;
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unsigned int clkpost;
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unsigned int clkpre;
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unsigned int clkprepare;
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unsigned int clksettle;
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unsigned int clktermen;
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unsigned int clktrail;
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unsigned int clkzero;
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unsigned int dtermen;
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unsigned int eot;
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unsigned int hsexit;
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unsigned int hsprepare;
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unsigned int hszero;
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unsigned int hssettle;
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unsigned int hsskip;
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unsigned int hstrail;
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unsigned int init;
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unsigned int lpx;
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unsigned int taget;
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unsigned int tago;
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unsigned int tasure;
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unsigned int wakeup;
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};
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struct inno_mipi_dphy_timing {
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u8 lpx;
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u8 hs_prepare;
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u8 hs_zero;
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u8 hs_trail;
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u8 hs_exit;
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u8 clk_post;
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u8 wakup_h;
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u8 wakup_l;
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u8 clk_pre;
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u8 ta_go;
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u8 ta_sure;
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u8 ta_wait;
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};
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struct inno_mipi_dphy {
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struct udevice *dev;
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void __iomem *regs;
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unsigned int lane_mbps;
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int lanes;
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};
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static const u32 lane_reg_offset[] = {
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[CLOCK_LANE] = INNO_CLOCK_LANE_REG_BASE,
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[DATA_LANE_0] = INNO_DATA_LANE_0_REG_BASE,
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[DATA_LANE_1] = INNO_DATA_LANE_1_REG_BASE,
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[DATA_LANE_2] = INNO_DATA_LANE_2_REG_BASE,
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[DATA_LANE_3] = INNO_DATA_LANE_3_REG_BASE,
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};
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#define FIXED_PARAM(_freq, _lpx, _prepare, _clk_zero, _data_zero, _trail) \
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{ \
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.max_freq = _freq, \
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.lpx = _lpx, \
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.hs_prepare = _prepare, \
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.clk_lane = { \
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.hs_zero = _clk_zero, \
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}, \
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.data_lane = { \
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.hs_zero = _data_zero, \
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}, \
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.hs_trail = _trail, \
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}
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struct fixed_param {
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unsigned int max_freq;
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u8 lpx;
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u8 hs_prepare;
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struct {
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u8 hs_zero;
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} clk_lane;
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struct {
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u8 hs_zero;
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} data_lane;
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u8 hs_trail;
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};
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static const struct fixed_param fixed_param_table[] = {
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FIXED_PARAM(110, 0x0, 0x20, 0x16, 0x02, 0x22),
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FIXED_PARAM(150, 0x0, 0x06, 0x16, 0x03, 0x45),
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FIXED_PARAM(200, 0x0, 0x18, 0x17, 0x04, 0x0b),
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FIXED_PARAM(250, 0x0, 0x05, 0x17, 0x05, 0x16),
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FIXED_PARAM(300, 0x0, 0x51, 0x18, 0x06, 0x2c),
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FIXED_PARAM(400, 0x0, 0x64, 0x19, 0x07, 0x33),
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FIXED_PARAM(500, 0x0, 0x20, 0x1b, 0x07, 0x4e),
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FIXED_PARAM(600, 0x0, 0x6a, 0x1d, 0x08, 0x3a),
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FIXED_PARAM(700, 0x0, 0x3e, 0x1e, 0x08, 0x6a),
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FIXED_PARAM(800, 0x0, 0x21, 0x1f, 0x09, 0x29),
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FIXED_PARAM(1000, 0x0, 0x09, 0x20, 0x09, 0x27)
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};
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static const struct fixed_param rk1808_fixed_param_table[] = {
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FIXED_PARAM(110, 0x02, 0x7f, 0x16, 0x02, 0x02),
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FIXED_PARAM(150, 0x02, 0x7f, 0x16, 0x03, 0x02),
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FIXED_PARAM(200, 0x02, 0x7f, 0x17, 0x04, 0x02),
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FIXED_PARAM(250, 0x02, 0x7f, 0x17, 0x05, 0x04),
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FIXED_PARAM(300, 0x02, 0x7f, 0x18, 0x06, 0x04),
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FIXED_PARAM(400, 0x03, 0x7e, 0x19, 0x07, 0x04),
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FIXED_PARAM(500, 0x03, 0x7c, 0x1b, 0x07, 0x08),
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FIXED_PARAM(600, 0x03, 0x70, 0x1d, 0x08, 0x10),
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FIXED_PARAM(700, 0x05, 0x40, 0x1e, 0x08, 0x30),
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FIXED_PARAM(800, 0x05, 0x02, 0x1f, 0x09, 0x30),
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FIXED_PARAM(1000, 0x05, 0x08, 0x20, 0x09, 0x30),
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FIXED_PARAM(1400, 0x09, 0x03, 0x32, 0x14, 0x0f),
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FIXED_PARAM(1600, 0x0d, 0x42, 0x36, 0x0e, 0x0f),
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FIXED_PARAM(1800, 0x0e, 0x47, 0x7a, 0x0e, 0x0f),
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FIXED_PARAM(2000, 0x11, 0x64, 0x7a, 0x0e, 0x0b),
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};
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static inline void inno_write(struct inno_mipi_dphy *inno, u32 reg, u32 val)
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{
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writel(val, inno->regs + reg);
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}
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static inline u32 inno_read(struct inno_mipi_dphy *inno, u32 reg)
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{
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return readl(inno->regs + reg);
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}
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static inline void inno_update_bits(struct inno_mipi_dphy *inno, u32 reg,
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u32 mask, u32 val)
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{
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u32 tmp, orig;
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orig = inno_read(inno, reg);
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tmp = orig & ~mask;
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tmp |= val & mask;
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inno_write(inno, reg, tmp);
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}
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static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
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unsigned long period)
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{
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/* Global Operation Timing Parameters */
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timing->clkmiss = 0;
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timing->clkpost = 70 + 52 * period;
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timing->clkpre = 8 * period;
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timing->clkprepare = 65;
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timing->clksettle = 95;
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timing->clktermen = 0;
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timing->clktrail = 80;
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timing->clkzero = 260;
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timing->dtermen = 0;
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timing->eot = 0;
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timing->hsexit = 120;
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timing->hsprepare = 65 + 4 * period;
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timing->hszero = 145 + 6 * period;
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timing->hssettle = 85 + 6 * period;
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timing->hsskip = 40;
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timing->hstrail = max(8 * period, 60 + 4 * period);
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timing->init = 100000;
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timing->lpx = 60;
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timing->taget = 5 * timing->lpx;
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timing->tago = 4 * timing->lpx;
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timing->tasure = 2 * timing->lpx;
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timing->wakeup = 1000000;
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}
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static void inno_mipi_dphy_timing_update(struct inno_mipi_dphy *inno,
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enum lane_type lane_type,
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struct inno_mipi_dphy_timing *t)
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{
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u32 base = lane_reg_offset[lane_type];
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u32 m, v;
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m = T_HS_PREPARE_MASK;
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v = T_HS_PREPARE(t->hs_prepare);
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inno_update_bits(inno, base + T_HS_PREPARE_OFFSET, m, v);
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m = T_HS_ZERO_MASK;
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v = T_HS_ZERO(t->hs_zero);
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inno_update_bits(inno, base + T_HS_ZERO_OFFSET, m, v);
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m = T_HS_TRAIL_MASK;
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v = T_HS_TRAIL(t->hs_trail);
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inno_update_bits(inno, base + T_HS_TRAIL_OFFSET, m, v);
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m = T_HS_EXIT_MASK;
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v = T_HS_EXIT(t->hs_exit);
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inno_update_bits(inno, base + T_HS_EXIT_OFFSET, m, v);
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if (lane_type == CLOCK_LANE) {
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m = T_CLK_POST_MASK;
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v = T_CLK_POST(t->clk_post);
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inno_update_bits(inno, base + T_CLK_POST_OFFSET, m, v);
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m = T_CLK_PRE_MASK;
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v = T_CLK_PRE(t->clk_pre);
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inno_update_bits(inno, base + T_CLK_PRE_OFFSET, m, v);
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}
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m = T_WAKUP_H_MASK;
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v = T_WAKUP_H(t->wakup_h);
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inno_update_bits(inno, base + T_WAKUP_H_OFFSET, m, v);
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m = T_WAKUP_L_MASK;
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v = T_WAKUP_L(t->wakup_l);
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inno_update_bits(inno, base + T_WAKUP_L_OFFSET, m, v);
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m = T_LPX_MASK;
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v = T_LPX(t->lpx);
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inno_update_bits(inno, base + T_LPX_OFFSET, m, v);
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m = T_TA_GO_MASK;
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v = T_TA_GO(t->ta_go);
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inno_update_bits(inno, base + T_TA_GO_OFFSET, m, v);
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m = T_TA_SURE_MASK;
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v = T_TA_SURE(t->ta_sure);
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inno_update_bits(inno, base + T_TA_SURE_OFFSET, m, v);
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m = T_TA_WAIT_MASK;
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v = T_TA_WAIT(t->ta_wait);
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inno_update_bits(inno, base + T_TA_WAIT_OFFSET, m, v);
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}
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static void inno_mipi_dphy_get_fixed_param(struct inno_mipi_dphy_timing *t,
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unsigned int freq,
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enum soc_type soc_type,
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enum lane_type lane_type)
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{
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const struct fixed_param *param, *param_table;
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int i, param_num;
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if (soc_type == RK1808_MIPI_DPHY) {
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param_table = rk1808_fixed_param_table;
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param_num = ARRAY_SIZE(rk1808_fixed_param_table);
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} else {
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param_table = fixed_param_table;
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param_num = ARRAY_SIZE(fixed_param_table);
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}
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for (i = 0; i < param_num; i++)
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if (freq <= param_table[i].max_freq)
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break;
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if (i == param_num)
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--i;
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param = ¶m_table[i];
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if (lane_type == CLOCK_LANE)
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t->hs_zero = param->clk_lane.hs_zero;
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else
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t->hs_zero = param->data_lane.hs_zero;
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t->hs_prepare = param->hs_prepare;
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t->hs_trail = param->hs_trail;
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if (soc_type == RK1808_MIPI_DPHY)
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t->lpx = param->lpx;
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}
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static void inno_mipi_dphy_lane_timing_init(struct inno_mipi_dphy *inno,
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enum lane_type lane_type)
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{
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struct rockchip_phy *phy =
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(struct rockchip_phy *)dev_get_driver_data(inno->dev);
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struct mipi_dphy_timing timing;
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struct inno_mipi_dphy_timing data;
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unsigned long txbyteclk, txclkesc, UI;
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unsigned int esc_clk_div;
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memset(&timing, 0, sizeof(timing));
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memset(&data, 0, sizeof(data));
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txbyteclk = inno->lane_mbps * USEC_PER_SEC / 8;
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esc_clk_div = DIV_ROUND_UP(txbyteclk, 20000000);
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txclkesc = txbyteclk / esc_clk_div;
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UI = DIV_ROUND_CLOSEST(NSEC_PER_USEC, inno->lane_mbps);
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debug("txbyteclk=%lu, txclkesc=%lu, esc_clk_div=%u, UI=%lu\n",
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txbyteclk, txclkesc, esc_clk_div, UI);
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mipi_dphy_timing_get_default(&timing, UI);
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inno_mipi_dphy_get_fixed_param(&data, inno->lane_mbps,
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phy->soc_type, lane_type);
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/*
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* Ttxbyteclk * val >= Ths-exit
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* Ttxbyteclk * val >= Tclk-post
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* Ttxbyteclk * val >= Tclk-pre
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* Ttxbyteclk * (2 + val) >= Tlpx
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*/
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data.hs_exit = DIV_ROUND_UP(timing.hsexit * txbyteclk, NSEC_PER_SEC);
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data.clk_post = DIV_ROUND_UP(timing.clkpost * txbyteclk, NSEC_PER_SEC);
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data.clk_pre = DIV_ROUND_UP(timing.clkpre * txbyteclk, NSEC_PER_SEC);
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data.wakup_h = 0x3;
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data.wakup_l = 0xff;
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if (phy->soc_type == RV1108_MIPI_DPHY) {
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data.lpx = DIV_ROUND_UP(txbyteclk * timing.lpx, NSEC_PER_SEC);
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if (data.lpx > 2)
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data.lpx -= 2;
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}
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/*
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* Ttxclkesc * val >= Tta-go
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* Ttxclkesc * val >= Tta-sure
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* Ttxclkesc * val >= Tta-wait
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*/
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data.ta_go = DIV_ROUND_UP(timing.tago * txclkesc, NSEC_PER_SEC);
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data.ta_sure = DIV_ROUND_UP(timing.tasure * txclkesc, NSEC_PER_SEC);
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data.ta_wait = DIV_ROUND_UP(timing.taget * txclkesc, NSEC_PER_SEC);
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inno_mipi_dphy_timing_update(inno, lane_type, &data);
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#define TIMING_NS(x, freq) (((x) * (DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq))))
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debug("hs-exit=%lu, clk-post=%lu, clk-pre=%lu, lpx=%lu\n",
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TIMING_NS(data.hs_exit, txbyteclk),
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TIMING_NS(data.clk_post, txbyteclk),
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TIMING_NS(data.clk_pre, txbyteclk),
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TIMING_NS(data.lpx + 2, txbyteclk));
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debug("ta-go=%lu, ta-sure=%lu, ta-wait=%lu\n",
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TIMING_NS(data.ta_go, txclkesc),
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TIMING_NS(data.ta_sure, txclkesc),
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TIMING_NS(data.ta_wait, txclkesc));
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}
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static unsigned long inno_mipi_dphy_pll_round_rate(unsigned long fin,
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unsigned long fout,
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u8 *prediv, u16 *fbdiv)
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{
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unsigned long best_freq = 0;
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u8 min_prediv, max_prediv;
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u8 _prediv, best_prediv = 0;
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u16 _fbdiv, best_fbdiv = 0;
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u32 min_delta = 0xffffffff;
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fout *= 2;
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min_prediv = DIV_ROUND_UP(fin, 40000000);
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max_prediv = fin / 5000000;
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for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
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u64 tmp;
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u32 delta;
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tmp = (u64)fout * _prediv;
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do_div(tmp, fin);
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_fbdiv = tmp;
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if ((_fbdiv == 15) || (_fbdiv < 12) || (_fbdiv > 511))
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continue;
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tmp = (u64)_fbdiv * fin;
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do_div(tmp, _prediv);
|
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delta = abs(fout - tmp);
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if (delta < min_delta) {
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best_prediv = _prediv;
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best_fbdiv = _fbdiv;
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min_delta = delta;
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best_freq = tmp;
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}
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}
|
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if (best_freq) {
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*prediv = best_prediv;
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*fbdiv = best_fbdiv;
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}
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return best_freq / 2;
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}
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static inline void inno_mipi_dphy_reset(struct inno_mipi_dphy *inno)
|
{
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/* Reset analog */
|
inno_update_bits(inno, INNO_PHY_POWER_CTRL,
|
ANALOG_RESET_MASK, ANALOG_RESET);
|
udelay(1);
|
inno_update_bits(inno, INNO_PHY_POWER_CTRL,
|
ANALOG_RESET_MASK, ANALOG_NORMAL);
|
/* Reset digital */
|
inno_update_bits(inno, INNO_PHY_DIG_CTRL,
|
DIGITAL_RESET_MASK, DIGITAL_RESET);
|
udelay(1);
|
inno_update_bits(inno, INNO_PHY_DIG_CTRL,
|
DIGITAL_RESET_MASK, DIGITAL_NORMAL);
|
}
|
|
static void inno_mipi_dphy_timing_init(struct inno_mipi_dphy *inno)
|
{
|
switch (inno->lanes) {
|
case 4:
|
inno_mipi_dphy_lane_timing_init(inno, DATA_LANE_3);
|
/* Fall through */
|
case 3:
|
inno_mipi_dphy_lane_timing_init(inno, DATA_LANE_2);
|
/* Fall through */
|
case 2:
|
inno_mipi_dphy_lane_timing_init(inno, DATA_LANE_1);
|
/* Fall through */
|
case 1:
|
default:
|
inno_mipi_dphy_lane_timing_init(inno, DATA_LANE_0);
|
inno_mipi_dphy_lane_timing_init(inno, CLOCK_LANE);
|
break;
|
}
|
}
|
|
static inline void inno_mipi_dphy_lane_enable(struct inno_mipi_dphy *inno)
|
{
|
u32 m = 0, v = 0;
|
|
switch (inno->lanes) {
|
case 4:
|
m |= DATA_LANE_3_EN_MASK;
|
v |= DATA_LANE_3_EN;
|
/* Fall through */
|
case 3:
|
m |= DATA_LANE_2_EN_MASK;
|
v |= DATA_LANE_2_EN;
|
/* Fall through */
|
case 2:
|
m |= DATA_LANE_1_EN_MASK;
|
v |= DATA_LANE_1_EN;
|
/* Fall through */
|
default:
|
case 1:
|
m |= DATA_LANE_0_EN_MASK | CLK_LANE_EN_MASK;
|
v |= DATA_LANE_0_EN | CLK_LANE_EN;
|
break;
|
}
|
|
inno_update_bits(inno, INNO_PHY_LANE_CTRL, m, v);
|
}
|
|
static inline void inno_mipi_dphy_pll_ldo_disable(struct inno_mipi_dphy *inno)
|
{
|
inno_update_bits(inno, INNO_PHY_POWER_CTRL,
|
PLL_POWER_MASK | LDO_POWER_MASK,
|
PLL_POWER_DOWN | LDO_POWER_DOWN);
|
}
|
|
static inline void inno_mipi_dphy_pll_ldo_enable(struct inno_mipi_dphy *inno)
|
{
|
inno_update_bits(inno, INNO_PHY_POWER_CTRL,
|
PLL_POWER_MASK | LDO_POWER_MASK,
|
PLL_POWER_ON | LDO_POWER_ON);
|
}
|
|
static inline void inno_mipi_dphy_da_pwrok_enable(struct inno_mipi_dphy *inno)
|
{
|
inno_update_bits(inno, INNO_PHY_LANE_CTRL, PWROK_BP | PWROK, PWROK);
|
}
|
|
static inline void inno_mipi_dphy_da_pwrok_disable(struct inno_mipi_dphy *inno)
|
{
|
inno_update_bits(inno, INNO_PHY_LANE_CTRL, PWROK_BP | PWROK, PWROK_BP);
|
}
|
|
static inline void inno_mipi_dphy_bgpd_enable(struct inno_mipi_dphy *inno)
|
{
|
inno_update_bits(inno, INNO_PHY_LANE_CTRL, MIPI_BGPD, 0);
|
}
|
|
static inline void inno_mipi_dphy_bgpd_disable(struct inno_mipi_dphy *inno)
|
{
|
inno_update_bits(inno, INNO_PHY_LANE_CTRL, MIPI_BGPD, MIPI_BGPD);
|
inno_update_bits(inno, INNO_PHY_LVDS_CTRL, LVDS_BGPD, LVDS_BGPD);
|
}
|
|
static int inno_mipi_dphy_power_on(struct rockchip_phy *phy)
|
{
|
struct inno_mipi_dphy *inno = dev_get_priv(phy->dev);
|
|
inno_mipi_dphy_bgpd_enable(inno);
|
inno_mipi_dphy_da_pwrok_enable(inno);
|
inno_mipi_dphy_pll_ldo_enable(inno);
|
inno_mipi_dphy_lane_enable(inno);
|
inno_mipi_dphy_reset(inno);
|
inno_mipi_dphy_timing_init(inno);
|
udelay(1);
|
|
return 0;
|
}
|
|
static inline void inno_mipi_dphy_lane_disable(struct inno_mipi_dphy *inno)
|
{
|
inno_update_bits(inno, INNO_PHY_LANE_CTRL, 0x7c, 0x00);
|
}
|
|
static int inno_mipi_dphy_power_off(struct rockchip_phy *phy)
|
{
|
struct inno_mipi_dphy *inno = dev_get_priv(phy->dev);
|
|
inno_mipi_dphy_lane_disable(inno);
|
inno_mipi_dphy_pll_ldo_disable(inno);
|
inno_mipi_dphy_da_pwrok_disable(inno);
|
inno_mipi_dphy_bgpd_disable(inno);
|
|
return 0;
|
}
|
|
static unsigned long inno_mipi_dphy_set_pll(struct rockchip_phy *phy,
|
unsigned long rate)
|
{
|
struct inno_mipi_dphy *inno = dev_get_priv(phy->dev);
|
unsigned long fin, fout;
|
u16 fbdiv = 0;
|
u8 prediv = 0;
|
u32 m, v;
|
|
fin = 24000000;
|
fout = inno_mipi_dphy_pll_round_rate(fin, rate, &prediv, &fbdiv);
|
|
debug("%s: fin=%lu, fout=%lu, prediv=%u, fbdiv=%u\n",
|
__func__, fin, fout, prediv, fbdiv);
|
|
m = FBDIV_HI_MASK | PREDIV_MASK;
|
v = FBDIV_HI(fbdiv >> 8) | PREDIV(prediv);
|
inno_update_bits(inno, INNO_PHY_PLL_CTRL_0, m, v);
|
|
m = FBDIV_LO_MASK;
|
v = FBDIV_LO(fbdiv);
|
inno_update_bits(inno, INNO_PHY_PLL_CTRL_1, m, v);
|
|
if (phy->soc_type == RK1808_MIPI_DPHY) {
|
inno_update_bits(inno, ANALOG_REG_08,
|
PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
|
inno_update_bits(inno, ANALOG_REG_0B,
|
CLOCK_LANE_VOD_RANGE_SET_MASK,
|
CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
|
}
|
|
inno->lane_mbps = fout / USEC_PER_SEC;
|
|
return fout;
|
}
|
|
static int inno_mipi_dphy_parse_dt(struct inno_mipi_dphy *inno)
|
{
|
struct udevice *dev = inno->dev;
|
|
inno->lanes = ofnode_read_u32_default(dev->node, "inno,lanes", 4);
|
|
return 0;
|
}
|
|
static int inno_mipi_dphy_init(struct rockchip_phy *phy)
|
{
|
struct inno_mipi_dphy *inno = dev_get_priv(phy->dev);
|
int ret;
|
|
ret = inno_mipi_dphy_parse_dt(inno);
|
if (ret) {
|
printf("%s: failed to parse DT\n", __func__);
|
return ret;
|
}
|
|
inno->regs = dev_read_addr_ptr(inno->dev);
|
|
return 0;
|
}
|
|
static const struct rockchip_phy_funcs inno_mipi_dphy_funcs = {
|
.init = inno_mipi_dphy_init,
|
.power_on = inno_mipi_dphy_power_on,
|
.power_off = inno_mipi_dphy_power_off,
|
.set_pll = inno_mipi_dphy_set_pll,
|
};
|
|
static const struct udevice_id inno_mipi_dphy_ids[] = {
|
{
|
.compatible = "rockchip,rv1108-mipi-dphy",
|
},
|
{
|
.compatible = "rockchip,rk1808-mipi-dphy",
|
},
|
{
|
.compatible = "rockchip,rv1126-mipi-dphy",
|
},
|
{}
|
};
|
|
static int inno_mipi_dphy_probe(struct udevice *dev)
|
{
|
struct inno_mipi_dphy *inno = dev_get_priv(dev);
|
struct rockchip_phy *phy;
|
|
phy = calloc(1, sizeof(*phy));
|
if (!phy)
|
return -ENOMEM;
|
|
dev->driver_data = (ulong)phy;
|
inno->dev = dev;
|
phy->dev = dev;
|
phy->funcs = &inno_mipi_dphy_funcs;
|
|
#if defined(CONFIG_ROCKCHIP_RV1108)
|
phy->soc_type = RV1108_MIPI_DPHY;
|
#else
|
phy->soc_type = RK1808_MIPI_DPHY;
|
#endif
|
|
return 0;
|
}
|
|
U_BOOT_DRIVER(inno_mipi_dphy) = {
|
.name = "inno_mipi_dphy",
|
.id = UCLASS_PHY,
|
.of_match = inno_mipi_dphy_ids,
|
.probe = inno_mipi_dphy_probe,
|
.priv_auto_alloc_size = sizeof(struct inno_mipi_dphy),
|
};
|
