/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ADDI_TCW_H
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#define _ADDI_TCW_H
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/*
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* Following are the generic definitions for the ADDI-DATA timer/counter/
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* watchdog (TCW) registers and bits. Some of the registers are not used
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* depending on the use of the TCW.
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*/
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#define ADDI_TCW_VAL_REG 0x00
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#define ADDI_TCW_SYNC_REG 0x00
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#define ADDI_TCW_SYNC_CTR_TRIG BIT(8)
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#define ADDI_TCW_SYNC_CTR_DIS BIT(7)
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#define ADDI_TCW_SYNC_CTR_ENA BIT(6)
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#define ADDI_TCW_SYNC_TIMER_TRIG BIT(5)
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#define ADDI_TCW_SYNC_TIMER_DIS BIT(4)
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#define ADDI_TCW_SYNC_TIMER_ENA BIT(3)
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#define ADDI_TCW_SYNC_WDOG_TRIG BIT(2)
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#define ADDI_TCW_SYNC_WDOG_DIS BIT(1)
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#define ADDI_TCW_SYNC_WDOG_ENA BIT(0)
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#define ADDI_TCW_RELOAD_REG 0x04
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#define ADDI_TCW_TIMEBASE_REG 0x08
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#define ADDI_TCW_CTRL_REG 0x0c
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#define ADDI_TCW_CTRL_EXT_CLK_STATUS BIT(21)
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#define ADDI_TCW_CTRL_CASCADE BIT(20)
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#define ADDI_TCW_CTRL_CNTR_ENA BIT(19)
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#define ADDI_TCW_CTRL_CNT_UP BIT(18)
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#define ADDI_TCW_CTRL_EXT_CLK(x) (((x) & 3) << 16)
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#define ADDI_TCW_CTRL_EXT_CLK_MASK ADDI_TCW_CTRL_EXT_CLK(3)
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#define ADDI_TCW_CTRL_MODE(x) (((x) & 7) << 13)
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#define ADDI_TCW_CTRL_MODE_MASK ADDI_TCW_CTRL_MODE(7)
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#define ADDI_TCW_CTRL_OUT(x) (((x) & 3) << 11)
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#define ADDI_TCW_CTRL_OUT_MASK ADDI_TCW_CTRL_OUT(3)
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#define ADDI_TCW_CTRL_GATE BIT(10)
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#define ADDI_TCW_CTRL_TRIG BIT(9)
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#define ADDI_TCW_CTRL_EXT_GATE(x) (((x) & 3) << 7)
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#define ADDI_TCW_CTRL_EXT_GATE_MASK ADDI_TCW_CTRL_EXT_GATE(3)
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#define ADDI_TCW_CTRL_EXT_TRIG(x) (((x) & 3) << 5)
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#define ADDI_TCW_CTRL_EXT_TRIG_MASK ADDI_TCW_CTRL_EXT_TRIG(3)
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#define ADDI_TCW_CTRL_TIMER_ENA BIT(4)
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#define ADDI_TCW_CTRL_RESET_ENA BIT(3)
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#define ADDI_TCW_CTRL_WARN_ENA BIT(2)
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#define ADDI_TCW_CTRL_IRQ_ENA BIT(1)
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#define ADDI_TCW_CTRL_ENA BIT(0)
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#define ADDI_TCW_STATUS_REG 0x10
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#define ADDI_TCW_STATUS_SOFT_CLR BIT(3)
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#define ADDI_TCW_STATUS_HARDWARE_TRIG BIT(2)
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#define ADDI_TCW_STATUS_SOFT_TRIG BIT(1)
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#define ADDI_TCW_STATUS_OVERFLOW BIT(0)
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#define ADDI_TCW_IRQ_REG 0x14
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#define ADDI_TCW_IRQ BIT(0)
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#define ADDI_TCW_WARN_TIMEVAL_REG 0x18
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#define ADDI_TCW_WARN_TIMEBASE_REG 0x1c
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#endif
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