/*
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* Allwinner A31 SoCs pinctrl driver.
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*
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* Copyright (C) 2014 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-sunxi.h"
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static const struct sunxi_desc_pin sun6i_a31_pins[] = {
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D0 */
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SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D1 */
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SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D2 */
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SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D3 */
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SUNXI_FUNCTION(0x4, "uart1"), /* RING */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D4 */
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SUNXI_FUNCTION(0x4, "uart1"), /* TX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D5 */
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SUNXI_FUNCTION(0x4, "uart1"), /* RX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D6 */
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SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D7 */
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SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D8 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D9 */
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SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
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SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D10 */
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SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
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SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D11 */
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SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
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SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D12 */
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SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
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SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D13 */
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SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
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SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D14 */
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SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
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SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D15 */
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SUNXI_FUNCTION(0x4, "clk_out_a"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D16 */
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SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D17 */
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SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D18 */
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SUNXI_FUNCTION(0x4, "clk_out_b"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D19 */
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SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D20 */
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SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D21 */
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SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D22 */
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SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* COL */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* D23 */
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SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* CLK */
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SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* DE */
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SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
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SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
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PINCTRL_SUN6I_A31), /* HSYNC */
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SUNXI_FUNCTION(0x4, "clk_out_c"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
|
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
|
PINCTRL_SUN6I_A31), /* VSYNC */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
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SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
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SUNXI_FUNCTION_VARIANT(0x4, "csi",
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PINCTRL_SUN6I_A31), /* MCLK1 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
|
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
|
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
|
SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
|
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
|
SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
|
/* Hole */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
|
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
|
SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
|
SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0")), /* RE */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
|
SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
|
SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
|
SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
|
SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
|
SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
|
SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
|
SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
|
SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
|
SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
|
SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
|
SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
|
SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
|
SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
|
SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
|
SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
|
SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
|
SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
|
SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
|
SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
|
SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
|
/* Hole in pin numbering for A31s */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 16), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */
|
SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 17), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */
|
SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 18), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */
|
SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 19), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */
|
SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 20), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */
|
SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 21), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */
|
SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 22), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */
|
SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 23), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */
|
SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
|
SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
|
SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
|
/* Hole */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
|
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
|
PINCTRL_SUN6I_A31)), /* VP0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
|
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
|
PINCTRL_SUN6I_A31)), /* VN0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
|
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
|
PINCTRL_SUN6I_A31)), /* VP1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
|
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
|
PINCTRL_SUN6I_A31)), /* VN1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
|
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
|
PINCTRL_SUN6I_A31)), /* VP2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
|
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
|
PINCTRL_SUN6I_A31)), /* VN2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
|
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
|
PINCTRL_SUN6I_A31)), /* VPC */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
|
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
|
PINCTRL_SUN6I_A31)), /* VNC */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
|
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
|
PINCTRL_SUN6I_A31)), /* VP3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
|
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
|
PINCTRL_SUN6I_A31)), /* VN3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
|
/* Hole */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
|
SUNXI_FUNCTION(0x3, "ts"), /* CLK */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
|
SUNXI_FUNCTION(0x3, "ts"), /* ERR */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
|
SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
|
SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
|
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
|
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
|
SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
|
SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
|
SUNXI_FUNCTION(0x3, "ts"), /* D0 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
|
SUNXI_FUNCTION(0x3, "ts"), /* D1 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
|
SUNXI_FUNCTION(0x3, "ts"), /* D2 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
|
SUNXI_FUNCTION(0x3, "ts"), /* D3 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D8 */
|
SUNXI_FUNCTION(0x3, "ts"), /* D4 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D9 */
|
SUNXI_FUNCTION(0x3, "ts"), /* D5 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D10 */
|
SUNXI_FUNCTION(0x3, "ts"), /* D6 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D11 */
|
SUNXI_FUNCTION(0x3, "ts"), /* D7 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 16), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* MIPI CSI MCLK */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */
|
/* Hole */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
|
SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
|
SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
|
SUNXI_FUNCTION(0x4, "uart0")), /* TX */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
|
SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
|
SUNXI_FUNCTION(0x4, "uart0")), /* RX */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
|
SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
|
/* Hole */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
|
SUNXI_FUNCTION_VARIANT(0x3, "usb",
|
PINCTRL_SUN6I_A31), /* DP3 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
|
SUNXI_FUNCTION_VARIANT(0x3, "usb",
|
PINCTRL_SUN6I_A31), /* DM3 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
|
SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
|
SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
|
SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
|
SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
|
SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart4"), /* TX */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart4"), /* RX */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
|
/* Hole; H starts at pin 9 for A31s */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 0), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand1")), /* WE */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 1), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand1")), /* ALE */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 2), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand1")), /* CLE */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 3), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 4), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 5), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand1")), /* RE */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 6), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 7), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 8), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
|
SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
|
SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
|
SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
|
SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
|
SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
|
SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
|
SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
|
SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "pwm0")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart0")), /* TX */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart0")), /* RX */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
/*
|
* The SPDIF block is not referenced at all in the A31 user
|
* manual. However it is described in the code leaked and the
|
* configuration files supplied by vendors.
|
*/
|
SUNXI_FUNCTION(0x3, "spdif")), /* SPDIF IN */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
/* Undocumented mux function - see above */
|
SUNXI_FUNCTION(0x3, "spdif")), /* SPDIF OUT */
|
/* 2 extra pins for A31 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 29), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */
|
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 30), PINCTRL_SUN6I_A31,
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
|
};
|
|
static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
|
.pins = sun6i_a31_pins,
|
.npins = ARRAY_SIZE(sun6i_a31_pins),
|
.irq_banks = 4,
|
.disable_strict_mode = true,
|
};
|
|
static int sun6i_a31_pinctrl_probe(struct platform_device *pdev)
|
{
|
unsigned long variant =
|
(unsigned long)of_device_get_match_data(&pdev->dev);
|
|
return sunxi_pinctrl_init_with_variant(pdev,
|
&sun6i_a31_pinctrl_data,
|
variant);
|
}
|
|
static const struct of_device_id sun6i_a31_pinctrl_match[] = {
|
{
|
.compatible = "allwinner,sun6i-a31-pinctrl",
|
.data = (void *)PINCTRL_SUN6I_A31
|
},
|
{
|
.compatible = "allwinner,sun6i-a31s-pinctrl",
|
.data = (void *)PINCTRL_SUN6I_A31S
|
},
|
{}
|
};
|
|
static struct platform_driver sun6i_a31_pinctrl_driver = {
|
.probe = sun6i_a31_pinctrl_probe,
|
.driver = {
|
.name = "sun6i-a31-pinctrl",
|
.of_match_table = sun6i_a31_pinctrl_match,
|
},
|
};
|
builtin_platform_driver(sun6i_a31_pinctrl_driver);
|
