/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
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*
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* Author: Shunqing Chen <csq@rock-chips.com>
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*/
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#ifndef __RK_HDMIRX_HDCP_H__
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#define __RK_HDMIRX_HDCP_H__
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#include <linux/miscdevice.h>
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#define HDCP_KEY_SIZE 308
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#define HDCP_KEY_SEED_SIZE 2
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#define KSV_LEN 5
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#define HEADER 10
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#define SHAMAX 20
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#define PRIVATE_KEY_SIZE 280
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#define KEY_SHA_SIZE 20
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#define KEY_DATA_SIZE 314
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#define VENDOR_DATA_SIZE (KEY_DATA_SIZE + 16)
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#define HDMIRX_HDCP1X_ID 13
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#define HDCP_SIG_MAGIC 0x4B534541 /* "AESK" */
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#define HDCP_FLG_AES 1
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enum hdmirx_hdcp_enable {
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HDCP_1X_ENABLE = 0x1,
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HDCP_2X_ENABLE = 0x2,
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};
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struct hdcp_key_data_t {
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unsigned int signature;
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unsigned int length;
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unsigned int crc;
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unsigned int flags;
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unsigned char data[0];
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};
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struct rk_hdmirx_hdcp {
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u8 enable;
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u8 hdcp_support;
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int hdcp2_enable;
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int status;
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struct miscdevice mdev;
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bool keys_is_load;
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bool test_key_load;
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bool aes_encrypt;
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struct device *dev;
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struct rk_hdmirx_dev *hdmirx;
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void (*write)(struct rk_hdmirx_dev *hdmirx, int reg, u32 val);
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u32 (*read)(struct rk_hdmirx_dev *hdmirx, int reg);
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void (*hpd_config)(struct rk_hdmirx_dev *hdmirx, bool en);
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bool (*tx_5v_power)(struct rk_hdmirx_dev *hdmirx);
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int (*hdcp_start)(struct rk_hdmirx_hdcp *hdcp);
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int (*hdcp_stop)(struct rk_hdmirx_hdcp *hdcp);
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void (*hdcp2_connect_ctrl)(struct rk_hdmirx_hdcp *hdcp, bool en);
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};
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struct rk_hdmirx_hdcp *rk_hdmirx_hdcp_register(struct rk_hdmirx_hdcp *hdcp);
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void rk_hdmirx_hdcp_unregister(struct rk_hdmirx_hdcp *hdcp);
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#endif /* __RK_HDMIRX_HDCP_H__ */
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