// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
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*
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* it66353 HDMI 3 in 1 out driver.
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*
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* Author: Kenneth.Hung@ite.com.tw
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* Wangqiang Guo <kay.guo@rock-chips.com>
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* Version: IT66353_SAMPLE_1.08
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*
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*/
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#ifndef _IT66353_DRV_H_
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#define _IT66353_DRV_H_
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#include "platform.h"
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#include "it66353.h"
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#define RX_PORT_0 0
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#define RX_PORT_1 1
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#define RX_PORT_2 2
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#define RX_PORT_3 3
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#define TRUE 1
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#define FALSE 0
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#define DDCWAITTIME 5
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#define DDCWAITNUM 10
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#define RX_PORT_COUNT 4
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// for it66353_rx_term_power_down
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#define CH0_OFF (0x10)
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#define CH1_OFF (0x20)
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#define CH2_OFF (0x40)
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#define CLK_OFF (0x80)
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#define ALLCH_OFF (0xF0)
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#define ALLCH_ON (0x00)
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/* ===================================================
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* config:
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* ===================================================
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*
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* RCLKFreqSel => 0: 20MHz, 1: 10MHz, 2: 5MHz, 3: 2.5MHz
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*/
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#define RCLKFreqSel 0
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typedef enum {
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RX_TOGGLE_HPD,
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RX_PORT_CHANGE,
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TX_OUTPUT,
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TX_OUTPUT_PREPARE,
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RX_CHECK_EQ,
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SETUP_AFE,
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RX_WAIT_CLOCK,
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RX_HPD,
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TX_GOT_HPD,
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TX_WAIT_HPD,
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TX_UNPLUG,
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RX_UNPLUG,
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IDLE,
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} _SYS_FSM_STATE;
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enum {
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HDMI_MODE_AUTO,
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HDMI_MODE_14,
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HDMI_MODE_20,
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};
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enum {
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EQ_MODE_H14,
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EQ_MODE_H20,
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};
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typedef enum {
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DEV_DEVICE_LOOP,
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DEV_DEVICE_INIT,
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DEV_WAIT_DEVICE_READY,
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DEV_FW_VAR_INIT,
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DEV_WAIT_RESET,
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} _DEV_FSM_STATE;
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typedef enum {
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AEQ_OFF,
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AEQ_START,
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AEQ_CHECK_SAREQ_RESULT,
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AEQ_APPLY_SAREQ,
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AEQ_DONE,
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AEQ_FAIL,
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AEQ_MAX,
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} _AEQ_FSM_STATE;
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typedef enum {
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EQRES_UNKNOWN,
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EQRES_BUSY,
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EQRES_SAREQ_DONE,
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EQRES_SAREQ_FAIL,
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EQRES_SAREQ_TIMEOUT,
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EQRES_H14EQ_DONE,
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EQRES_H14EQ_FAIL,
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EQRES_H14EQ_TIMEOUT,
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EQRES_DONE,
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} _EQ_RESULT_TYPE;
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typedef enum {
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SysAEQ_OFF,
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SysAEQ_RUN,
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SysAEQ_DONE,
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} _SYS_AEQ_TYPE;
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enum {
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EDID_SRC_EXT_SINK,
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EDID_SRC_INTERNAL,
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};
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enum {
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TERM_LOW,
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TERM_HIGH,
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TERM_FOLLOW_TX,
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TERM_FOLLOW_HPD,
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};
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#define EDID_PORT_0 0x01
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#define EDID_PORT_1 0x02
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#define EDID_PORT_2 0x04
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#define EDID_PORT_3 0x08
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#define EDID_PORT_ALL (EDID_PORT_0 | EDID_PORT_1 | EDID_PORT_2 | EDID_PORT_3)
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/*
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* for it66353_get_port_info0()
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*/
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#define PI_5V (BIT(0))
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#define PI_HDMI_MODE (BIT(1))
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#define PI_CLK_DET (BIT(2))
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#define PI_CLK_VALID (BIT(3))
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#define PI_CLK_STABLE (BIT(4))
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#define PI_PLL_LOCK (BIT(5))
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// #define PI_XX (BIT(6))
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#define PI_SYM_LOCK (BIT(7))
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/*
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* for it66353_get_port_info1()
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*/
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#define PI_PLL_HS1G 0x01
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// #define PI_PLL_HS1G (BIT0)
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typedef struct {
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// TxSwap
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u8 EnTxPNSwap;
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u8 EnTxChSwap;
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u8 EnTxVCLKInv;
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u8 EnTxOutD1t;
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u8 EnRxDDCBypass;
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u8 EnRxPWR5VBypass;
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u8 EnRxHPDBypass;
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u8 EnCEC;
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u8 EnableAutoEQ;
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u8 ParseEDIDFromSink;
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u8 NonActivePortReplyHPD;
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u8 DisableEdidRam;
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u8 TryFixedEQFirst;
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u8 TurnOffTx5VWhenSwitchPort;
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u8 FixIncorrectHdmiEnc;
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} IT6635_DEVICE_OPTION_INT;
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typedef struct {
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u8 tag1;
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u8 EnRxDDCBypass;
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u8 EnRxPWR5VBypass;
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u8 EnRxHPDBypass;
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u8 TryFixedEQFirst;
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u8 EnableAutoEQ;
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u8 NonActivePortReplyHPD;
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u8 DisableEdidRam;
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u8 DefaultEQ[3];
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u8 FixIncorrectHdmiEnc;
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u8 HPDOutputInverse;
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u8 HPDTogglePeriod;
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u8 TxOEAlignment;
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u8 str_size;
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} IT6635_RX_OPTIONS;
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typedef struct {
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u8 tag1;
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// TxSwap
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u8 EnTxPNSwap;
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u8 EnTxChSwap;
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u8 EnTxVCLKInv;
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u8 EnTxOutD1t;
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u8 CopyEDIDFromSink;
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u8 ParsePhysicalAddr;
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u8 TurnOffTx5VWhenSwitchPort;
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u8 str_size;
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} IT6635_TX_OPTIONS;
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typedef struct {
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u8 tag1;
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u8 SwAddr;
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u8 RxAddr;
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u8 CecAddr;
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u8 EdidAddr;
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u8 ForceRxOn;
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u8 RxAutoPowerDown;
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u8 DoTxPowerDown;
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u8 TxPowerDownWhileWaitingClock;
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u8 str_size;
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} IT6635_DEV_OPTION;
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typedef struct {
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IT6635_RX_OPTIONS *active_rx_opt;
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IT6635_RX_OPTIONS *rx_opt[4];
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IT6635_TX_OPTIONS *tx_opt;
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IT6635_DEV_OPTION *dev_opt;
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} IT6635_DEV_OPTION_INTERNAL;
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typedef struct {
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struct {
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u8 Rev;
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u32 RCLK;
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u8 RxHPDFlag[4];
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u8 VSDBOffset; // 0xFF;
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u8 PhyAdr[4];
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u8 EdidChkSum[2];
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_SYS_FSM_STATE state_sys_fsm;
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u8 state_dev_init;
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u8 state_dev;
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u8 fsm_return;
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u8 Rx_active_port;
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u8 Rx_new_port;
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u8 Tx_current_5v;
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u32 vclk;
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u32 vclk_prev;
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u16 RxCEDErr[3];
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u8 RxCEDErrValid;
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u16 RxCEDErrRec[3][3];
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u8 count_unlock;
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u8 count_symlock;
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u8 count_symlock_lost;
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u8 count_symlock_fail;
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u8 count_symlock_unstable;
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u8 count_fsm_err;
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u8 count_eq_check;
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u8 count_try_force_hdmi_mode;
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u8 count_auto_eq_fail;
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u8 count_wait_clock;
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u8 clock_ratio;
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u8 h2_scramble;
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u8 edid_ready;
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u8 prev_hpd_state;
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u8 try_fixed_EQ;
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u8 current_hdmi_mode;
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u8 current_txoe;
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u8 check_for_hpd_toggle;
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u8 sdi_stable_count;
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u8 check_for_sdi;
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u8 force_hpd_state;
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// u8 txoe_alignment;
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u8 hpd_toggle_timeout;
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u8 spmon;
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__tick tick_set_afe;
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__tick tick_hdcp;
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// u8 en_count_hdcp;
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u8 *default_edid[4];
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// tx
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u8 hpd_wait_count;
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u8 is_hdmi20_sink;
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u8 rx_deskew_err;
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} vars;
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struct {
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_SYS_AEQ_TYPE sys_aEQ;
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u8 AutoEQ_state;
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u8 AutoEQ_WaitTime;
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u8 AutoEQ_Result;
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u8 DFE_Valid;
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u8 RS_Valid;
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u16 RS_ValidMap[3];
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u8 EqHDMIMode;
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u8 ManuEQ_state;
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u8 DFE[14][3][3]; // [RS_value][channel012][NumABC] -> 0x34B...0x353
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u8 CalcRS[3];
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u8 EQ_flag_14;
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u8 EQ_flag_20;
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u8 txoe_ready14;
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u8 txoe_ready20;
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u8 stored_RS_14[3];
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u8 stored_RS_20[3];
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u8 current_eq_mode;
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// u8 FixedRsIndex[4];
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u8 meq_cur_idx;
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u8 meq_adj_idx[3];
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u32 ced_err_avg[3];
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u32 ced_err_avg_prev[3];
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u8 ced_acc_count;
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u8 manu_eq_fine_tune_count[3];
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u8 manu_eq_fine_tune_best_rs[3];
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} EQ;
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// u8 edid_buf[128];
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IT6635_DEV_OPTION_INTERNAL opts;
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} IT6635_DEVICE_DATA;
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extern IT6635_DEVICE_DATA it66353_gdev;
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extern const u8 it66353_rs_value[];
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extern IT6635_RX_OPTIONS it66353_s_RxOpts;
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extern IT6635_TX_OPTIONS it66353_s_TxOpts;
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extern IT6635_DEV_OPTION it66353_s_DevOpts;
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extern u8 it66353_s_default_edid_port0[];
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#ifdef __cplusplus
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extern "C" {
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#endif
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// --------------------------------
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extern u8 it66353_h2swwr(u8 offset, u8 wdata);
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extern u8 it66353_h2swrd(u8 offset);
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extern u8 it66353_h2swset(u8 offset, u8 mask, u8 wdata);
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extern void it66353_h2swbrd(u8 offset, u8 length, u8 *rddata);
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extern void it66353_h2swbwr(u8 offset, u8 length, u8 *rddata);
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extern u8 it66353_h2rxwr(u8 offset, u8 wdata);
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extern u8 it66353_h2rxrd(u8 offset);
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extern u8 it66353_h2rxset(u8 offset, u8 mask, u8 dwata);
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extern void it66353_h2rxbrd(u8 offset, u8 length, u8 *rddata);
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extern void it66353_h2rxbwr(u8 offset, u8 length, u8 *rddata);
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extern u8 it66353_cecwr(u8 offset, u8 wdata);
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extern u8 it66353_cecrd(u8 offset);
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extern u8 it66353_cecset(u8 offset, u8 mask, u8 wdata);
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extern void it66353_cecbrd(u8 offset, u8 length, u8 *rddata);
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extern void it66353_cecbwr(u8 offset, u8 length, u8 *rddata);
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extern u8 it66353_h2rxedidwr(u8 offset, u8 *wrdata, u8 length);
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extern void it66353_chgrxbank(u8 bankno);
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extern void it66353_chgswbank(u8 bankno);
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extern void it66353_rx_update_ced_err_from_hw(void);
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extern void it66353_rx_get_ced_err(void);
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extern void it66353_rx_clear_ced_err(void);
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extern u8 it66353_rx_monitor_ced_err(void);
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extern void it66353_rx_DFE_enable(u8 enable);
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extern void it66353_rx_set_rs_3ch(u8 *rs_value);
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extern void it66353_rx_set_rs(u8 ch, u8 rs_value);
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extern u8 it66353_rx_is_all_ch_symlock(void);
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extern u8 it66353_rx_is_ch_symlock(u8 ch);
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extern u8 it66353_rx_is_clock_stable(void);
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extern void it66353_rx_ovwr_hdmi_clk(u8 port, u8 ratio);
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extern void it66353_rx_ovwr_h20_scrb(u8 port, u8 scrb);
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extern void it66353_rx_auto_power_down_enable(u8 port, u8 enable);
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extern void it66353_rx_term_power_down(u8 port, u8 channel);
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extern void it66353_rx_handle_output_err(void);
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extern void it66353_sw_enable_timer0(void);
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extern void it66353_sw_disable_timer0(void);
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extern u8 it66353_sw_get_timer0_interrupt(void);
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extern void it66353_sw_clear_hdcp_status(void);
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// --------------------------------
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extern void it66353_txoe(u8 enable);
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extern void it66353_auto_detect_hdmi_encoding(void);
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extern void it66353_fix_incorrect_hdmi_encoding(void);
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extern u8 it66353_get_port_info1(u8 port, u8 info);
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extern u8 it66353_get_port_info0(u8 port, u8 info);
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extern void it66353_init_rclk(void);
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extern void it66353_enable_tx_port(u8 enable);
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// --------------
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extern void it66353_sys_state(u8 new_state);
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extern void it66353_rx_reset(void);
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extern void it66353_rx_caof_init(u8 port);
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extern void it66353_eq_save_h20(void);
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extern void it66353_eq_load_h20(void);
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extern void it66353_eq_save_h14(void);
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extern void it66353_eq_load_h14(void);
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extern void it66353_eq_load_previous(void);
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extern void it66353_eq_load_default(void);
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extern void it66353_eq_reset_state(void);
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extern void it66353_eq_set_state(u8 state);
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extern u8 it66353_eq_get_state(void);
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extern void it66353_eq_reset_txoe_ready(void);
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extern void it66353_eq_set_txoe_ready(u8 ready);
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extern u8 it66353_eq_get_txoe_ready(void);
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extern void it66353_aeq_set_DFE2(u8 EQ0, u8 EQ1, u8 EQ2);
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extern u8 it66353_rx_is_hdmi20(void);
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extern void it66353_aeq_diable_eq_trigger(void);
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extern u8 it66353_aeq_check_sareq_result(void);
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#if DEBUG_FSM_CHANGE
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#define it66353_fsm_chg(new_state) __it66353_fsm_chg(new_state, __LINE__)
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#define it66353_fsm_chg_delayed(new_state) __it66353_fsm_chg2(new_state, __LINE__)
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#else
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extern void it66353_fsm_chg(u8 new_state);
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extern void it66353_fsm_chg_delayed(u8 new_state);
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#endif
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extern void __it66353_fsm_chg(u8 new_state, int caller);
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extern void __it66353_fsm_chg2(u8 new_state, int caller);
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// void it66353_vars_init(void);
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extern bool it66353_device_init(void);
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extern bool it66353_device_init2(void);
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extern bool it66353_read_edid(u8 block, u8 offset, int length, u8 *edid_buffer);
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extern bool it66353_write_one_block_edid(u8 block, u8 *edid_buffer);
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extern bool it66353_setup_edid_ram(u8 flag);
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extern void it66353_force_hdmi20(void);
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#ifdef __cplusplus
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}
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#endif
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extern void it66353_rx_skew_adj(u8 ch);
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#define _rx_edid_address_enable(port)\
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{it66353_h2swset(0x55 + port, 0x24, 0x20); }
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#define _rx_edid_address_disable(port)\
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{it66353_h2swset(0x55 + port, 0x24, 0x04); }
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#define _rx_edid_ram_enable(port)\
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{if (it66353_gdev.opts.rx_opt[port]->EnRxDDCBypass == 0) { it66353_h2swset(0x55 + port, 0x01, 0x00); }}
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#define _rx_edid_ram_disable(port)\
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{ it66353_h2swset(0x55 + port, 0x01, 0x01); }
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#define _rx_edid_set_chksum(port, sum)\
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{ it66353_h2swwr(0xe1 + port * 2, sum); }
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#define _rx_edid_set_cec_phyaddr(port, phyAB, phyCD)\
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{ it66353_h2swwr(0xd9 + port*2, phyAB); it66353_h2swwr(0xda + port*2, phyCD); }
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#endif
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