/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* specific defines for CCD's HFC 2BDS0 PCI chips
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*
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* Author Werner Cornelius (werner@isdn4linux.de)
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*
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* Copyright 1999 by Werner Cornelius (werner@isdn4linux.de)
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*/
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/*
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* thresholds for transparent B-channel mode
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* change mask and threshold simultaneously
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*/
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#define HFCPCI_BTRANS_THRESHOLD 128
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#define HFCPCI_FILLEMPTY 64
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#define HFCPCI_BTRANS_THRESMASK 0x00
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/* defines for PCI config */
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#define PCI_ENA_MEMIO 0x02
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#define PCI_ENA_MASTER 0x04
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/* GCI/IOM bus monitor registers */
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#define HCFPCI_C_I 0x08
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#define HFCPCI_TRxR 0x0C
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#define HFCPCI_MON1_D 0x28
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#define HFCPCI_MON2_D 0x2C
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/* GCI/IOM bus timeslot registers */
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#define HFCPCI_B1_SSL 0x80
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#define HFCPCI_B2_SSL 0x84
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#define HFCPCI_AUX1_SSL 0x88
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#define HFCPCI_AUX2_SSL 0x8C
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#define HFCPCI_B1_RSL 0x90
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#define HFCPCI_B2_RSL 0x94
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#define HFCPCI_AUX1_RSL 0x98
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#define HFCPCI_AUX2_RSL 0x9C
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/* GCI/IOM bus data registers */
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#define HFCPCI_B1_D 0xA0
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#define HFCPCI_B2_D 0xA4
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#define HFCPCI_AUX1_D 0xA8
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#define HFCPCI_AUX2_D 0xAC
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/* GCI/IOM bus configuration registers */
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#define HFCPCI_MST_EMOD 0xB4
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#define HFCPCI_MST_MODE 0xB8
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#define HFCPCI_CONNECT 0xBC
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/* Interrupt and status registers */
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#define HFCPCI_FIFO_EN 0x44
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#define HFCPCI_TRM 0x48
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#define HFCPCI_B_MODE 0x4C
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#define HFCPCI_CHIP_ID 0x58
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#define HFCPCI_CIRM 0x60
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#define HFCPCI_CTMT 0x64
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#define HFCPCI_INT_M1 0x68
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#define HFCPCI_INT_M2 0x6C
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#define HFCPCI_INT_S1 0x78
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#define HFCPCI_INT_S2 0x7C
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#define HFCPCI_STATUS 0x70
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/* S/T section registers */
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#define HFCPCI_STATES 0xC0
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#define HFCPCI_SCTRL 0xC4
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#define HFCPCI_SCTRL_E 0xC8
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#define HFCPCI_SCTRL_R 0xCC
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#define HFCPCI_SQ 0xD0
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#define HFCPCI_CLKDEL 0xDC
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#define HFCPCI_B1_REC 0xF0
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#define HFCPCI_B1_SEND 0xF0
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#define HFCPCI_B2_REC 0xF4
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#define HFCPCI_B2_SEND 0xF4
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#define HFCPCI_D_REC 0xF8
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#define HFCPCI_D_SEND 0xF8
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#define HFCPCI_E_REC 0xFC
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/* bits in status register (READ) */
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#define HFCPCI_PCI_PROC 0x02
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#define HFCPCI_NBUSY 0x04
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#define HFCPCI_TIMER_ELAP 0x10
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#define HFCPCI_STATINT 0x20
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#define HFCPCI_FRAMEINT 0x40
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#define HFCPCI_ANYINT 0x80
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/* bits in CTMT (Write) */
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#define HFCPCI_CLTIMER 0x80
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#define HFCPCI_TIM3_125 0x04
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#define HFCPCI_TIM25 0x10
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#define HFCPCI_TIM50 0x14
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#define HFCPCI_TIM400 0x18
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#define HFCPCI_TIM800 0x1C
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#define HFCPCI_AUTO_TIMER 0x20
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#define HFCPCI_TRANSB2 0x02
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#define HFCPCI_TRANSB1 0x01
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/* bits in CIRM (Write) */
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#define HFCPCI_AUX_MSK 0x07
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#define HFCPCI_RESET 0x08
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#define HFCPCI_B1_REV 0x40
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#define HFCPCI_B2_REV 0x80
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/* bits in INT_M1 and INT_S1 */
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#define HFCPCI_INTS_B1TRANS 0x01
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#define HFCPCI_INTS_B2TRANS 0x02
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#define HFCPCI_INTS_DTRANS 0x04
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#define HFCPCI_INTS_B1REC 0x08
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#define HFCPCI_INTS_B2REC 0x10
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#define HFCPCI_INTS_DREC 0x20
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#define HFCPCI_INTS_L1STATE 0x40
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#define HFCPCI_INTS_TIMER 0x80
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/* bits in INT_M2 */
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#define HFCPCI_PROC_TRANS 0x01
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#define HFCPCI_GCI_I_CHG 0x02
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#define HFCPCI_GCI_MON_REC 0x04
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#define HFCPCI_IRQ_ENABLE 0x08
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#define HFCPCI_PMESEL 0x80
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/* bits in STATES */
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#define HFCPCI_STATE_MSK 0x0F
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#define HFCPCI_LOAD_STATE 0x10
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#define HFCPCI_ACTIVATE 0x20
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#define HFCPCI_DO_ACTION 0x40
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#define HFCPCI_NT_G2_G3 0x80
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/* bits in HFCD_MST_MODE */
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#define HFCPCI_MASTER 0x01
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#define HFCPCI_SLAVE 0x00
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#define HFCPCI_F0IO_POSITIV 0x02
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#define HFCPCI_F0_NEGATIV 0x04
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#define HFCPCI_F0_2C4 0x08
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/* remaining bits are for codecs control */
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/* bits in HFCD_SCTRL */
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#define SCTRL_B1_ENA 0x01
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#define SCTRL_B2_ENA 0x02
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#define SCTRL_MODE_TE 0x00
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#define SCTRL_MODE_NT 0x04
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#define SCTRL_LOW_PRIO 0x08
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#define SCTRL_SQ_ENA 0x10
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#define SCTRL_TEST 0x20
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#define SCTRL_NONE_CAP 0x40
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#define SCTRL_PWR_DOWN 0x80
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/* bits in SCTRL_E */
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#define HFCPCI_AUTO_AWAKE 0x01
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#define HFCPCI_DBIT_1 0x04
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#define HFCPCI_IGNORE_COL 0x08
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#define HFCPCI_CHG_B1_B2 0x80
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/* bits in FIFO_EN register */
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#define HFCPCI_FIFOEN_B1 0x03
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#define HFCPCI_FIFOEN_B2 0x0C
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#define HFCPCI_FIFOEN_DTX 0x10
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#define HFCPCI_FIFOEN_B1TX 0x01
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#define HFCPCI_FIFOEN_B1RX 0x02
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#define HFCPCI_FIFOEN_B2TX 0x04
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#define HFCPCI_FIFOEN_B2RX 0x08
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/* definitions of fifo memory area */
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#define MAX_D_FRAMES 15
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#define MAX_B_FRAMES 31
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#define B_SUB_VAL 0x200
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#define B_FIFO_SIZE (0x2000 - B_SUB_VAL)
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#define D_FIFO_SIZE 512
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#define D_FREG_MASK 0xF
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struct zt {
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__le16 z1; /* Z1 pointer 16 Bit */
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__le16 z2; /* Z2 pointer 16 Bit */
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};
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struct dfifo {
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u_char data[D_FIFO_SIZE]; /* FIFO data space */
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u_char fill1[0x20A0 - D_FIFO_SIZE]; /* reserved, do not use */
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u_char f1, f2; /* f pointers */
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u_char fill2[0x20C0 - 0x20A2]; /* reserved, do not use */
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/* mask index with D_FREG_MASK for access */
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struct zt za[MAX_D_FRAMES + 1];
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u_char fill3[0x4000 - 0x2100]; /* align 16K */
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};
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struct bzfifo {
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struct zt za[MAX_B_FRAMES + 1]; /* only range 0x0..0x1F allowed */
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u_char f1, f2; /* f pointers */
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u_char fill[0x2100 - 0x2082]; /* alignment */
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};
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union fifo_area {
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struct {
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struct dfifo d_tx; /* D-send channel */
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struct dfifo d_rx; /* D-receive channel */
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} d_chan;
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struct {
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u_char fill1[0x200];
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u_char txdat_b1[B_FIFO_SIZE];
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struct bzfifo txbz_b1;
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struct bzfifo txbz_b2;
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u_char txdat_b2[B_FIFO_SIZE];
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u_char fill2[D_FIFO_SIZE];
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u_char rxdat_b1[B_FIFO_SIZE];
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struct bzfifo rxbz_b1;
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struct bzfifo rxbz_b2;
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u_char rxdat_b2[B_FIFO_SIZE];
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} b_chans;
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u_char fill[32768];
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};
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#define Write_hfc(a, b, c) (writeb(c, (a->hw.pci_io) + b))
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#define Read_hfc(a, b) (readb((a->hw.pci_io) + b))
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