/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Intel(R) Trace Hub Global Trace Hub (GTH) data structures
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*
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* Copyright (C) 2014-2015 Intel Corporation.
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*/
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#ifndef __INTEL_TH_GTH_H__
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#define __INTEL_TH_GTH_H__
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/* Map output port parameter bits to symbolic names */
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#define TH_OUTPUT_PARM(name) \
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TH_OUTPUT_ ## name
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enum intel_th_output_parm {
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/* output port type */
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TH_OUTPUT_PARM(port),
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/* generate NULL packet */
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TH_OUTPUT_PARM(null),
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/* packet drop */
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TH_OUTPUT_PARM(drop),
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/* port in reset state */
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TH_OUTPUT_PARM(reset),
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/* flush out data */
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TH_OUTPUT_PARM(flush),
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/* mainenance packet frequency */
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TH_OUTPUT_PARM(smcfreq),
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};
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/*
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* Register offsets
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*/
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enum {
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REG_GTH_GTHOPT0 = 0x00, /* Output ports 0..3 config */
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REG_GTH_GTHOPT1 = 0x04, /* Output ports 4..7 config */
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REG_GTH_SWDEST0 = 0x08, /* Switching destination masters 0..7 */
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REG_GTH_GSWTDEST = 0x88, /* Global sw trace destination */
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REG_GTH_SMCR0 = 0x9c, /* STP mainenance for ports 0/1 */
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REG_GTH_SMCR1 = 0xa0, /* STP mainenance for ports 2/3 */
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REG_GTH_SMCR2 = 0xa4, /* STP mainenance for ports 4/5 */
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REG_GTH_SMCR3 = 0xa8, /* STP mainenance for ports 6/7 */
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REG_GTH_SCR = 0xc8, /* Source control (storeEn override) */
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REG_GTH_STAT = 0xd4, /* GTH status */
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REG_GTH_SCR2 = 0xd8, /* Source control (force storeEn off) */
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REG_GTH_DESTOVR = 0xdc, /* Destination override */
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REG_GTH_SCRPD0 = 0xe0, /* ScratchPad[0] */
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REG_GTH_SCRPD1 = 0xe4, /* ScratchPad[1] */
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REG_GTH_SCRPD2 = 0xe8, /* ScratchPad[2] */
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REG_GTH_SCRPD3 = 0xec, /* ScratchPad[3] */
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REG_TSCU_TSUCTRL = 0x2000, /* TSCU control register */
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REG_TSCU_TSCUSTAT = 0x2004, /* TSCU status register */
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/* Common Capture Sequencer (CTS) registers */
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REG_CTS_C0S0_EN = 0x30c0, /* clause_event_enable_c0s0 */
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REG_CTS_C0S0_ACT = 0x3180, /* clause_action_control_c0s0 */
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REG_CTS_STAT = 0x32a0, /* cts_status */
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REG_CTS_CTL = 0x32a4, /* cts_control */
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};
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/* waiting for Pipeline Empty bit(s) to assert for GTH */
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#define GTH_PLE_WAITLOOP_DEPTH 10000
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#define TSUCTRL_CTCRESYNC BIT(0)
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#define TSCUSTAT_CTCSYNCING BIT(1)
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/* waiting for Trigger status to assert for CTS */
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#define CTS_TRIG_WAITLOOP_DEPTH 10000
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#define CTS_EVENT_ENABLE_IF_ANYTHING BIT(31)
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#define CTS_ACTION_CONTROL_STATE_OFF 27
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#define CTS_ACTION_CONTROL_SET_STATE(x) \
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(((x) & 0x1f) << CTS_ACTION_CONTROL_STATE_OFF)
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#define CTS_ACTION_CONTROL_TRIGGER BIT(4)
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#define CTS_STATE_IDLE 0x10u
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#define CTS_CTL_SEQUENCER_ENABLE BIT(0)
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#endif /* __INTEL_TH_GTH_H__ */
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