/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ZynqMP DPSUB Subsystem Driver
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*
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* Copyright (C) 2017 - 2020 Xilinx, Inc.
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*
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* Authors:
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* - Hyun Woo Kwon <hyun.kwon@xilinx.com>
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* - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#ifndef _ZYNQMP_DPSUB_H_
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#define _ZYNQMP_DPSUB_H_
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struct clk;
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struct device;
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struct drm_device;
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struct zynqmp_disp;
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struct zynqmp_dp;
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enum zynqmp_dpsub_format {
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ZYNQMP_DPSUB_FORMAT_RGB,
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ZYNQMP_DPSUB_FORMAT_YCRCB444,
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ZYNQMP_DPSUB_FORMAT_YCRCB422,
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ZYNQMP_DPSUB_FORMAT_YONLY,
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};
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/**
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* struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
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* @drm: The DRM/KMS device
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* @dev: The physical device
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* @apb_clk: The APB clock
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* @disp: The display controller
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* @dp: The DisplayPort controller
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* @dma_align: DMA alignment constraint (must be a power of 2)
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*/
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struct zynqmp_dpsub {
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struct drm_device drm;
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struct device *dev;
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struct clk *apb_clk;
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struct zynqmp_disp *disp;
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struct zynqmp_dp *dp;
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unsigned int dma_align;
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};
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static inline struct zynqmp_dpsub *to_zynqmp_dpsub(struct drm_device *drm)
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{
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return container_of(drm, struct zynqmp_dpsub, drm);
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}
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#endif /* _ZYNQMP_DPSUB_H_ */
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