/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dmub_reg.h"
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#include "../dmub_srv.h"
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struct dmub_reg_value_masks {
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uint32_t value;
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uint32_t mask;
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};
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static inline void
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set_reg_field_value_masks(struct dmub_reg_value_masks *field_value_mask,
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uint32_t value, uint32_t mask, uint8_t shift)
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{
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field_value_mask->value =
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(field_value_mask->value & ~mask) | (mask & (value << shift));
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field_value_mask->mask = field_value_mask->mask | mask;
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}
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static void set_reg_field_values(struct dmub_reg_value_masks *field_value_mask,
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uint32_t addr, int n, uint8_t shift1,
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uint32_t mask1, uint32_t field_value1,
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va_list ap)
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{
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uint32_t shift, mask, field_value;
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int i = 1;
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/* gather all bits value/mask getting updated in this register */
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set_reg_field_value_masks(field_value_mask, field_value1, mask1,
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shift1);
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while (i < n) {
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shift = va_arg(ap, uint32_t);
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mask = va_arg(ap, uint32_t);
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field_value = va_arg(ap, uint32_t);
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set_reg_field_value_masks(field_value_mask, field_value, mask,
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shift);
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i++;
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}
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}
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static inline uint32_t get_reg_field_value_ex(uint32_t reg_value, uint32_t mask,
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uint8_t shift)
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{
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return (mask & reg_value) >> shift;
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}
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void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,
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uint32_t mask1, uint32_t field_value1, ...)
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{
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struct dmub_reg_value_masks field_value_mask = { 0 };
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uint32_t reg_val;
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va_list ap;
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va_start(ap, field_value1);
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set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
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field_value1, ap);
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va_end(ap);
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reg_val = srv->funcs.reg_read(srv->user_ctx, addr);
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reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
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srv->funcs.reg_write(srv->user_ctx, addr, reg_val);
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}
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void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,
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uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...)
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{
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struct dmub_reg_value_masks field_value_mask = { 0 };
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va_list ap;
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va_start(ap, field_value1);
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set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
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field_value1, ap);
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va_end(ap);
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reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
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srv->funcs.reg_write(srv->user_ctx, addr, reg_val);
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}
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void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,
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uint32_t mask, uint32_t *field_value)
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{
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uint32_t reg_val = srv->funcs.reg_read(srv->user_ctx, addr);
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*field_value = get_reg_field_value_ex(reg_val, mask, shift);
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}
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