/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/mach-sa1100/include/mach/nanoengine.h
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*
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* This file contains the hardware specific definitions for nanoEngine.
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* Only include this file from SA1100-specific files.
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*
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* Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
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*/
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#ifndef __ASM_ARCH_NANOENGINE_H
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#define __ASM_ARCH_NANOENGINE_H
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#include <mach/irqs.h>
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#define GPIO_PC_READY0 11 /* ready for socket 0 (active high)*/
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#define GPIO_PC_READY1 12 /* ready for socket 1 (active high) */
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#define GPIO_PC_CD0 13 /* detect for socket 0 (active low) */
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#define GPIO_PC_CD1 14 /* detect for socket 1 (active low) */
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#define GPIO_PC_RESET0 15 /* reset socket 0 */
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#define GPIO_PC_RESET1 16 /* reset socket 1 */
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#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0
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#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11
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#define NANOENGINE_IRQ_GPIO_PC_READY1 IRQ_GPIO12
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#define NANOENGINE_IRQ_GPIO_PC_CD0 IRQ_GPIO13
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#define NANOENGINE_IRQ_GPIO_PC_CD1 IRQ_GPIO14
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/*
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* nanoEngine Memory Map:
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*
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* 0000.0000 - 003F.0000 - 4 MB Flash
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* C000.0000 - C1FF.FFFF - 32 MB SDRAM
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* 1860.0000 - 186F.FFFF - 1 MB Internal PCI Memory Read/Write
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* 18A1.0000 - 18A1.FFFF - 64 KB Internal PCI Config Space
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* 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode
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* 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode
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*
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*/
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#define NANO_PCI_MEM_RW_PHYS 0x18600000
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#define NANO_PCI_MEM_RW_VIRT 0xf1000000
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#define NANO_PCI_MEM_RW_SIZE SZ_1M
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#define NANO_PCI_CONFIG_SPACE_PHYS 0x18A10000
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#define NANO_PCI_CONFIG_SPACE_VIRT 0xf2000000
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#define NANO_PCI_CONFIG_SPACE_SIZE SZ_64K
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#endif
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