// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
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* stmmac XGMAC support.
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*/
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#include "stmmac.h"
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#include "dwxgmac2.h"
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static void dwxgmac2_core_init(struct mac_device_info *hw,
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struct net_device *dev)
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{
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void __iomem *ioaddr = hw->pcsr;
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int mtu = dev->mtu;
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u32 tx, rx;
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tx = readl(ioaddr + XGMAC_TX_CONFIG);
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rx = readl(ioaddr + XGMAC_RX_CONFIG);
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tx |= XGMAC_CORE_INIT_TX;
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rx |= XGMAC_CORE_INIT_RX;
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if (mtu >= 9000) {
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rx |= XGMAC_CONFIG_GPSLCE;
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rx |= XGMAC_JUMBO_LEN << XGMAC_CONFIG_GPSL_SHIFT;
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rx |= XGMAC_CONFIG_WD;
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} else if (mtu > 2000) {
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rx |= XGMAC_CONFIG_JE;
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} else if (mtu > 1500) {
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rx |= XGMAC_CONFIG_S2KP;
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}
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if (hw->ps) {
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tx |= XGMAC_CONFIG_TE;
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tx &= ~hw->link.speed_mask;
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switch (hw->ps) {
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case SPEED_10000:
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tx |= hw->link.speed10000;
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break;
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case SPEED_2500:
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tx |= hw->link.speed2500;
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break;
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case SPEED_1000:
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default:
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tx |= hw->link.speed1000;
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break;
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}
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}
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writel(tx, ioaddr + XGMAC_TX_CONFIG);
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writel(rx, ioaddr + XGMAC_RX_CONFIG);
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writel(XGMAC_INT_DEFAULT_EN, ioaddr + XGMAC_INT_EN);
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}
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static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable)
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{
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u32 tx = readl(ioaddr + XGMAC_TX_CONFIG);
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u32 rx = readl(ioaddr + XGMAC_RX_CONFIG);
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if (enable) {
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tx |= XGMAC_CONFIG_TE;
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rx |= XGMAC_CONFIG_RE;
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} else {
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tx &= ~XGMAC_CONFIG_TE;
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rx &= ~XGMAC_CONFIG_RE;
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}
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writel(tx, ioaddr + XGMAC_TX_CONFIG);
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writel(rx, ioaddr + XGMAC_RX_CONFIG);
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}
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static int dwxgmac2_rx_ipc(struct mac_device_info *hw)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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value = readl(ioaddr + XGMAC_RX_CONFIG);
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if (hw->rx_csum)
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value |= XGMAC_CONFIG_IPC;
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else
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value &= ~XGMAC_CONFIG_IPC;
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writel(value, ioaddr + XGMAC_RX_CONFIG);
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return !!(readl(ioaddr + XGMAC_RX_CONFIG) & XGMAC_CONFIG_IPC);
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}
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static void dwxgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,
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u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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value = readl(ioaddr + XGMAC_RXQ_CTRL0) & ~XGMAC_RXQEN(queue);
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if (mode == MTL_QUEUE_AVB)
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value |= 0x1 << XGMAC_RXQEN_SHIFT(queue);
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else if (mode == MTL_QUEUE_DCB)
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value |= 0x2 << XGMAC_RXQEN_SHIFT(queue);
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writel(value, ioaddr + XGMAC_RXQ_CTRL0);
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}
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static void dwxgmac2_rx_queue_prio(struct mac_device_info *hw, u32 prio,
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u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value, reg;
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reg = (queue < 4) ? XGMAC_RXQ_CTRL2 : XGMAC_RXQ_CTRL3;
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if (queue >= 4)
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queue -= 4;
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value = readl(ioaddr + reg);
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value &= ~XGMAC_PSRQ(queue);
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value |= (prio << XGMAC_PSRQ_SHIFT(queue)) & XGMAC_PSRQ(queue);
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writel(value, ioaddr + reg);
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}
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static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,
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u32 rx_alg)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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value = readl(ioaddr + XGMAC_MTL_OPMODE);
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value &= ~XGMAC_RAA;
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switch (rx_alg) {
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case MTL_RX_ALGORITHM_SP:
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break;
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case MTL_RX_ALGORITHM_WSP:
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value |= XGMAC_RAA;
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break;
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default:
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break;
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}
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writel(value, ioaddr + XGMAC_MTL_OPMODE);
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}
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static void dwxgmac2_prog_mtl_tx_algorithms(struct mac_device_info *hw,
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u32 tx_alg)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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value = readl(ioaddr + XGMAC_MTL_OPMODE);
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value &= ~XGMAC_ETSALG;
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switch (tx_alg) {
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case MTL_TX_ALGORITHM_WRR:
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value |= XGMAC_WRR;
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break;
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case MTL_TX_ALGORITHM_WFQ:
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value |= XGMAC_WFQ;
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break;
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case MTL_TX_ALGORITHM_DWRR:
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value |= XGMAC_DWRR;
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break;
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default:
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break;
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}
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writel(value, ioaddr + XGMAC_MTL_OPMODE);
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}
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static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue,
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u32 chan)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value, reg;
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reg = (queue < 4) ? XGMAC_MTL_RXQ_DMA_MAP0 : XGMAC_MTL_RXQ_DMA_MAP1;
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if (queue >= 4)
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queue -= 4;
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value = readl(ioaddr + reg);
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value &= ~XGMAC_QxMDMACH(queue);
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value |= (chan << XGMAC_QxMDMACH_SHIFT(queue)) & XGMAC_QxMDMACH(queue);
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writel(value, ioaddr + reg);
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}
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static int dwxgmac2_host_irq_status(struct mac_device_info *hw,
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struct stmmac_extra_stats *x)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 stat, en;
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en = readl(ioaddr + XGMAC_INT_EN);
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stat = readl(ioaddr + XGMAC_INT_STATUS);
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stat &= en;
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if (stat & XGMAC_PMTIS) {
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x->irq_receive_pmt_irq_n++;
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readl(ioaddr + XGMAC_PMT);
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}
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return 0;
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}
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static int dwxgmac2_host_mtl_irq_status(struct mac_device_info *hw, u32 chan)
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{
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void __iomem *ioaddr = hw->pcsr;
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int ret = 0;
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u32 status;
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status = readl(ioaddr + XGMAC_MTL_INT_STATUS);
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if (status & BIT(chan)) {
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u32 chan_status = readl(ioaddr + XGMAC_MTL_QINT_STATUS(chan));
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if (chan_status & XGMAC_RXOVFIS)
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ret |= CORE_IRQ_MTL_RX_OVERFLOW;
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writel(~0x0, ioaddr + XGMAC_MTL_QINT_STATUS(chan));
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}
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return ret;
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}
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static void dwxgmac2_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
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unsigned int fc, unsigned int pause_time,
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u32 tx_cnt)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 i;
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if (fc & FLOW_RX)
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writel(XGMAC_RFE, ioaddr + XGMAC_RX_FLOW_CTRL);
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if (fc & FLOW_TX) {
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for (i = 0; i < tx_cnt; i++) {
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u32 value = XGMAC_TFE;
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if (duplex)
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value |= pause_time << XGMAC_PT_SHIFT;
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writel(value, ioaddr + XGMAC_Qx_TX_FLOW_CTRL(i));
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}
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}
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}
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static void dwxgmac2_pmt(struct mac_device_info *hw, unsigned long mode)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 val = 0x0;
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if (mode & WAKE_MAGIC)
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val |= XGMAC_PWRDWN | XGMAC_MGKPKTEN;
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if (mode & WAKE_UCAST)
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val |= XGMAC_PWRDWN | XGMAC_GLBLUCAST | XGMAC_RWKPKTEN;
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if (val) {
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u32 cfg = readl(ioaddr + XGMAC_RX_CONFIG);
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cfg |= XGMAC_CONFIG_RE;
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writel(cfg, ioaddr + XGMAC_RX_CONFIG);
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}
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writel(val, ioaddr + XGMAC_PMT);
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}
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static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
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unsigned char *addr, unsigned int reg_n)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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value = (addr[5] << 8) | addr[4];
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writel(value | XGMAC_AE, ioaddr + XGMAC_ADDR0_HIGH);
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value = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
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writel(value, ioaddr + XGMAC_ADDR0_LOW);
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}
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static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,
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unsigned char *addr, unsigned int reg_n)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 hi_addr, lo_addr;
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/* Read the MAC address from the hardware */
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hi_addr = readl(ioaddr + XGMAC_ADDR0_HIGH);
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lo_addr = readl(ioaddr + XGMAC_ADDR0_LOW);
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/* Extract the MAC address from the high and low words */
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addr[0] = lo_addr & 0xff;
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addr[1] = (lo_addr >> 8) & 0xff;
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addr[2] = (lo_addr >> 16) & 0xff;
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addr[3] = (lo_addr >> 24) & 0xff;
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addr[4] = hi_addr & 0xff;
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addr[5] = (hi_addr >> 8) & 0xff;
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}
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static void dwxgmac2_set_filter(struct mac_device_info *hw,
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struct net_device *dev)
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{
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void __iomem *ioaddr = (void __iomem *)dev->base_addr;
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u32 value = XGMAC_FILTER_RA;
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if (dev->flags & IFF_PROMISC) {
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value |= XGMAC_FILTER_PR;
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} else if ((dev->flags & IFF_ALLMULTI) ||
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(netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
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value |= XGMAC_FILTER_PM;
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writel(~0x0, ioaddr + XGMAC_HASH_TABLE(0));
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writel(~0x0, ioaddr + XGMAC_HASH_TABLE(1));
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}
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writel(value, ioaddr + XGMAC_PACKET_FILTER);
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}
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const struct stmmac_ops dwxgmac210_ops = {
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.core_init = dwxgmac2_core_init,
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.set_mac = dwxgmac2_set_mac,
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.rx_ipc = dwxgmac2_rx_ipc,
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.rx_queue_enable = dwxgmac2_rx_queue_enable,
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.rx_queue_prio = dwxgmac2_rx_queue_prio,
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.tx_queue_prio = NULL,
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.rx_queue_routing = NULL,
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.prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,
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.prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,
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.set_mtl_tx_queue_weight = NULL,
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.map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,
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.config_cbs = NULL,
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.dump_regs = NULL,
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.host_irq_status = dwxgmac2_host_irq_status,
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.host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,
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.flow_ctrl = dwxgmac2_flow_ctrl,
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.pmt = dwxgmac2_pmt,
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.set_umac_addr = dwxgmac2_set_umac_addr,
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.get_umac_addr = dwxgmac2_get_umac_addr,
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.set_eee_mode = NULL,
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.reset_eee_mode = NULL,
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.set_eee_timer = NULL,
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.set_eee_pls = NULL,
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.pcs_ctrl_ane = NULL,
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.pcs_rane = NULL,
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.pcs_get_adv_lp = NULL,
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.debug = NULL,
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.set_filter = dwxgmac2_set_filter,
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};
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int dwxgmac2_setup(struct stmmac_priv *priv)
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{
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struct mac_device_info *mac = priv->hw;
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dev_info(priv->device, "\tXGMAC2\n");
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priv->dev->priv_flags |= IFF_UNICAST_FLT;
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mac->pcsr = priv->ioaddr;
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mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
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mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
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mac->mcast_bits_log2 = 0;
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if (mac->multicast_filter_bins)
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mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
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mac->link.duplex = 0;
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mac->link.speed10 = 0;
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mac->link.speed100 = 0;
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mac->link.speed1000 = XGMAC_CONFIG_SS_1000;
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mac->link.speed2500 = XGMAC_CONFIG_SS_2500;
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mac->link.speed10000 = XGMAC_CONFIG_SS_10000;
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mac->link.speed_mask = XGMAC_CONFIG_SS_MASK;
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mac->mii.addr = XGMAC_MDIO_ADDR;
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mac->mii.data = XGMAC_MDIO_DATA;
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mac->mii.addr_shift = 16;
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mac->mii.addr_mask = GENMASK(20, 16);
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mac->mii.reg_shift = 0;
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mac->mii.reg_mask = GENMASK(15, 0);
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mac->mii.clk_csr_shift = 19;
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mac->mii.clk_csr_mask = GENMASK(21, 19);
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return 0;
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}
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