/*
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*
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* Copyright 2015 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __HAL_H264D_RKV_REG_H__
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#define __HAL_H264D_RKV_REG_H__
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#include "mpp_hal.h"
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typedef struct h264d_rkv_regs_t {
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struct {
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RK_U32 minor_ver : 8;
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RK_U32 level : 1;
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RK_U32 dec_support : 3;
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RK_U32 profile : 1;
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RK_U32 reserve0 : 1;
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RK_U32 codec_flag : 1;
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RK_U32 reserve1 : 1;
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RK_U32 prod_num : 16;
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} sw00;
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struct {
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RK_U32 dec_e : 1;//0
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RK_U32 dec_clkgate_e : 1; // 1
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RK_U32 reserve0 : 1;// 2
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RK_U32 timeout_mode : 1; // 3
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RK_U32 dec_irq_dis : 1;//4 // 4
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RK_U32 dec_timeout_e : 1; //5
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RK_U32 buf_empty_en : 1; // 6
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RK_U32 stmerror_waitdecfifo_empty : 1; // 7
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RK_U32 dec_irq : 1; // 8
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RK_U32 dec_irq_raw : 1; // 9
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RK_U32 reserve2 : 2;
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RK_U32 dec_rdy_sta : 1; //12
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RK_U32 dec_bus_sta : 1; //13
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RK_U32 dec_error_sta : 1; // 14
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RK_U32 dec_timeout_sta : 1; //15
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RK_U32 dec_empty_sta : 1; // 16
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RK_U32 colmv_ref_error_sta : 1; // 17
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RK_U32 cabu_end_sta : 1; // 18
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RK_U32 h264orvp9_error_mode : 1; //19
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RK_U32 softrst_en_p : 1; //20
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RK_U32 force_softreset_valid : 1; //21
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RK_U32 softreset_rdy : 1; // 22
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RK_U32 reserve1 : 9;
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} sw01;
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struct {
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RK_U32 in_endian : 1;
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RK_U32 in_swap32_e : 1;
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RK_U32 in_swap64_e : 1;
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RK_U32 str_endian : 1;
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RK_U32 str_swap32_e : 1;
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RK_U32 str_swap64_e : 1;
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RK_U32 out_endian : 1;
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RK_U32 out_swap32_e : 1;
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RK_U32 out_cbcr_swap : 1;
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RK_U32 reserve0 : 1;
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RK_U32 rlc_mode_direct_write : 1;
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RK_U32 rlc_mode : 1;
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RK_U32 strm_start_bit : 7;
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RK_U32 reserve1 : 1;
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RK_U32 dec_mode : 2;
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RK_U32 reserve2 : 2;
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RK_U32 rps_mode : 1;
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RK_U32 stream_mode : 1;
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RK_U32 stream_lastpacket : 1;
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RK_U32 firstslice_flag : 1;
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RK_U32 frame_orslice : 1;
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RK_U32 buspr_slot_disable : 1;
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RK_U32 reverse3 : 2;
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} sw02;
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struct {
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RK_U32 y_hor_virstride : 9;
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RK_U32 reserve : 2;
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RK_U32 slice_num_highbit : 1;
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RK_U32 uv_hor_virstride : 9;
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RK_U32 slice_num_lowbits : 11;
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} sw03;
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struct {
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RK_U32 strm_rlc_base : 32;
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} sw04;
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struct {
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RK_U32 stream_len : 27;
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RK_U32 reverse0 : 5;
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} sw05;
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struct {
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RK_U32 cabactbl_base : 32;
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} sw06;
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struct {
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RK_U32 decout_base : 32;
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} sw07;
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struct {
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RK_U32 y_virstride : 20;
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RK_U32 reverse0 : 12;
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} sw08;
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struct {
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RK_U32 yuv_virstride : 21;
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RK_U32 reverse0 : 11;
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} sw09;
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struct {
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/* bit0: ref0_14_field
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* bit1: ref0_14_topfield_used
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* bit2: ref0_14_botfield_used
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* bit3: ref0_14_colmv_use_flag
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*/
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RK_U32 ref0_14_base; /* bit4-bit31 */
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} sw10_24[15];
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struct {
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RK_U32 ref0_14_poc : 32;
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} sw25_39[15];
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struct {
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RK_U32 cur_poc : 32;
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} sw40;
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struct {
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RK_U32 rlcwrite_base;
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} sw41;
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struct {
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RK_U32 pps_base;
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} sw42;
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struct {
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RK_U32 rps_base;
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} sw43;
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struct {
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RK_U32 strmd_error_e : 28;
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RK_U32 reserve : 4;
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} sw44;
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struct {
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RK_U32 strmd_error_status : 28;
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RK_U32 colmv_error_ref_picidx : 4;
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} sw45;
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struct {
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RK_U32 strmd_error_ctu_xoffset : 8;
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RK_U32 strmd_error_ctu_yoffset : 8;
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RK_U32 streamfifo_space2full : 7;
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RK_U32 reserve0 : 1;
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RK_U32 vp9_error_ctu0_en : 1;
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RK_U32 reverse1 : 7;
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} sw46;
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struct {
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RK_U32 saowr_xoffet : 9;
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RK_U32 reserve0 : 7;
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RK_U32 saowr_yoffset : 10;
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RK_U32 reverse1 : 6;
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} sw47;
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struct {
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/* bit0: ref15_field
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* bit1: ref15_topfield_used
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* bit2: ref15_botfield_used
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* bit3: ref15_colmv_use_flag
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*/
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RK_U32 ref15_base; /* bit4-bit31 */
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} sw48;
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struct {
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RK_U32 ref15_29_poc : 32;
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} sw49_63[15];
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struct {
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RK_U32 performance_cycle : 32;
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} sw64;
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struct {
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RK_U32 axi_ddr_rdata : 32;
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} sw65;
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struct {
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RK_U32 axi_ddr_rdata : 32;
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} sw66;
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struct {
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RK_U32 busifd_resetn : 1;
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RK_U32 cabac_resetn : 1;
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RK_U32 dec_ctrl_resetn : 1;
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RK_U32 transd_resetn : 1;
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RK_U32 intra_resetn : 1;
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RK_U32 inter_resetn : 1;
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RK_U32 recon_resetn : 1;
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RK_U32 filer_resetn : 1;
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RK_U32 reverse0 : 24;
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} sw67;
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struct {
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RK_U32 perf_cnt0_sel : 6;
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RK_U32 reserve0 : 2;
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RK_U32 perf_cnt1_sel : 6;
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RK_U32 reserve1 : 2;
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RK_U32 perf_cnt2_sel : 6;
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RK_U32 reverse1 : 10;
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} sw68;
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struct {
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RK_U32 perf_cnt0 : 32;
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} sw69;
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struct {
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RK_U32 perf_cnt1 : 32;
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} sw70;
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struct {
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RK_U32 perf_cnt2 : 32;
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} sw71;
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struct {
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RK_U32 ref30_poc;
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} sw72;
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struct {
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RK_U32 ref31_poc;
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} sw73;
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struct {
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RK_U32 cur_poc1 : 32;
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} sw74;
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struct {
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RK_U32 errorinfo_base : 32;
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} sw75;
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struct {
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RK_U32 slicedec_num : 14;
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RK_U32 reserve0 : 1;
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RK_U32 strmd_detect_error_flag : 1;
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RK_U32 error_packet_num : 14;
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RK_U32 reverse1 : 2;
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} sw76;
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struct {
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RK_U32 error_en_highbits : 30;
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RK_U32 reserve : 2;
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} sw77;
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RK_U32 reverse[2];
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} H264dRkvRegs_t;
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#ifdef __cplusplus
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extern "C" {
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#endif
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MPP_RET rkv_h264d_init (void *hal, MppHalCfg *cfg);
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MPP_RET rkv_h264d_deinit (void *hal);
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MPP_RET rkv_h264d_gen_regs(void *hal, HalTaskInfo *task);
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MPP_RET rkv_h264d_start (void *hal, HalTaskInfo *task);
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MPP_RET rkv_h264d_wait (void *hal, HalTaskInfo *task);
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MPP_RET rkv_h264d_reset (void *hal);
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MPP_RET rkv_h264d_flush (void *hal);
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MPP_RET rkv_h264d_control (void *hal, MpiCmd cmd_type, void *param);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HAL_H264D_RKV_REG_H__ */
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